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path: root/drivers/clk
AgeCommit message (Expand)Author
2020-05-14clk: qcom: gcc: Add GPU and NPU clocks for SM8150Vinod Koul
2020-05-14clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson
2020-05-14clk: qcom: gdsc: Handle GDSC regulator suppliesBjorn Andersson
2020-05-14clk: ti: dra7xx: fix RNG clock parentTero Kristo
2020-05-14clk: ti: dra7xx: mark MCAN clock as DRA76x onlyTero Kristo
2020-05-14clk: ti: dra7xx: fix gpu clkctrl parentTero Kristo
2020-05-14clk: ti: omap5: Add proper parent clocks for l4-secure clocksTero Kristo
2020-05-14clk: ti: omap4: Add proper parent clocks for l4-secure clocksTero Kristo
2020-05-14clk: ti: composite: fix memory leakTero Kristo
2020-05-13clk: vexpress-osc: Support building as a moduleRob Herring
2020-05-13clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542xMarek Szyprowski
2020-05-13clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski
2020-05-12clk: Move HAVE_CLK config out of architecture layerStephen Boyd
2020-05-12clk: ti: clkctrl: convert subclocks to use proper names alsoTero Kristo
2020-05-12clk: ti: am33xx: fix RTC clock parentTero Kristo
2020-05-12clk: ti: clkctrl: Fix Bad of_node_put within clkctrl_get_nameTero Kristo
2020-05-12Merge tag 'v5.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/ke...Stephen Boyd
2020-05-12clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding
2020-05-12clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding
2020-05-07clk: qoriq: add cpufreq platform deviceMian Yousaf Kaukab
2020-05-05clk: Allow the common clk framework to be selectableStephen Boyd
2020-05-05clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET
2020-05-05clk: Remove unused inline function clk_debug_reparentYueHaibing
2020-05-05clk: impd1: Look up clock-output-namesLinus Walleij
2020-05-05clk: Unlink clock if failed to prepare or enableMarc Zyngier
2020-05-05clk: vexpress-osc: Use the devres clock API variantsRob Herring
2020-05-05clk: versatile: Only enable SP810 on 32-bit by defaultRob Herring
2020-05-05clk: versatile: Rework kconfig structureRob Herring
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl
2020-04-30clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven
2020-04-30clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa
2020-04-28firmware: xilinx: Use APIs instead of IOCTLsRajan Vaja
2020-04-28firmware: xilinx: Remove eemi ops for clock set/get parentRajan Vaja