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path: root/drivers/dma
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2021-10-18dmaengine: imx-sdma: remove space after sizeofFlavio Suligoi
Space prohibited between function name and open parenthesis '(' Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Link: https://lore.kernel.org/r/20210928151833.589843-4-f.suligoi@asem.it Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: imx-sdma: align statement to open parenthesisFlavio Suligoi
Alignment should match open parenthesis. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Link: https://lore.kernel.org/r/20210928151833.589843-3-f.suligoi@asem.it Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: imx-sdma: add missed bracesFlavio Suligoi
The "if" conditional statement is not a single statement, so both branches require braces. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Link: https://lore.kernel.org/r/20210928151833.589843-2-f.suligoi@asem.it Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: imx-sdma: remove useless bracesFlavio Suligoi
Braces {} are not necessary for single statement blocks. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Link: https://lore.kernel.org/r/20210928151833.589843-1-f.suligoi@asem.it Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: dw-axi-dmac: set coherent maskPandith N
Add support for setting dma coherent mask, dma mask is set to 64 bit Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-4-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: dw-axi-dmac: Hardware handshake configurationPandith N
Added hardware handshake selection in channel config, for mem2per and per2mem case. The peripheral specific handshake interface needs to be programmed in src_per, dst_per bits of CHx_CFG register. Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-3-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8Pandith N
Added support for DMA controller with more than 8 channels. DMAC register map changes based on number of channels. Enabling DMAC channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHENREG2 has to be used when number of channels > 8 Configuring DMA channel: CHx_CFG has to be used when number of channels <= 8 CHx_CFG2 has to be used when number of channels > 8 Suspending and resuming channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHSUSPREG has to be used for suspending a channel > 8 Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-2-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: stm32-dma: fix burst in case of unaligned memory addressAmelie Delaunay
Theorically, address pointers used by STM32 DMA must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer. If this is always the case for peripheral addresses on STM32, it is not for memory addresses if the user doesn't respect this alignment constraint. To avoid a weird behavior of the DMA controller in this case (no error triggered but data are not transferred as expected), force no burst. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20211011094259.315023-4-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: stm32-dma: fix stm32_dma_get_max_widthAmelie Delaunay
buf_addr parameter of stm32_dma_set_xfer_param function is a dma_addr_t. We only need to check the remainder of buf_addr/max_width, so, no need to use do_div and extra u64 addr. Use '%' instead. Fixes: e0ebdbdcb42a ("dmaengine: stm32-dma: take address into account when computing max width") Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20211011094259.315023-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: stm32-dma: mark pending descriptor complete in terminate_allAmelie Delaunay
To prevent accidental repeated completion, mark pending descriptor complete in terminate_all. It can be the case when terminate_all is called while no end of transfer interrupt occurs. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20211011094259.315023-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: dw-edma: Remove an unused variableChristophe JAILLET
'head' is unused, remove it. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/46e071be21fbc5ac5c35d4796a7e4249e94c3a77.1633847306.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: jz4780: Set max number of SGs per burstArtur Rojek
Total amount of SG list entries executed in a single burst is limited by the number of available DMA descriptors. This information is useful for device drivers utilizing this DMA engine. Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210829195805.148964-1-contact@artur-rojek.eu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: sh: rz-dmac: Add DMA clock handlingBiju Das
Currently, DMA clocks are turned on by the bootloader. This patch adds support for DMA clock handling so that the driver manages the DMA clocks. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210923102451.11403-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: idxd: remove gen cap field per spec 1.2 updateDave Jiang
Remove max_descs_per_engine field. The recently released DSA spec 1.2 [1] has removed this field and made it reserved. [1]: https://software.intel.com/content/dam/develop/external/us/en/documents-tps/341204-intel-data-streaming-accelerator-spec.pdf Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/163406167978.1303649.1798682437841822837.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: idxd: check GENCAP config support for gencfg registerDave Jiang
DSA spec 1.2 has moved the GENCFG register under the GENCAP configuration support with respect to writability. Add check in driver before writing to GENCFG register. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/163406171896.1303830.11217958011385656998.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: bestcomm: fix system boot lockupsAnatolij Gustschin
memset() and memcpy() on an MMIO region like here results in a lockup at startup on mpc5200 platform (since this first happens during probing of the ATA and Ethernet drivers). Use memset_io() and memcpy_toio() instead. Fixes: 2f9ea1bde0d1 ("bestcomm: core bestcomm support for Freescale MPC5200") Cc: stable@vger.kernel.org # v5.14+ Signed-off-by: Anatolij Gustschin <agust@denx.de> Link: https://lore.kernel.org/r/20211014094012.21286-1-agust@denx.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: at_xdmac: use pm_ptr()Claudiu Beznea
Use pm_ptr() macro to fill at_xdmac_driver.driver.pm. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211007111230.2331837-5-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: at_xdmac: use __maybe_unused for pm functionsClaudiu Beznea
Use __maybe_unused for pm functions. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211007111230.2331837-4-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: at_xdmac: fix AT_XDMAC_CC_PERID() macroClaudiu Beznea
AT_XDMAC_CC_PERID() should be used to setup bits 24..30 of XDMAC_CC register. Using it without parenthesis around 0x7f & (i) will lead to setting all the time zero for bits 24..30 of XDMAC_CC as the << operator has higher precedence over bitwise &. Thus, add paranthesis around 0x7f & (i). Fixes: 15a03850ab8f ("dmaengine: at_xdmac: fix macro typo") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211007111230.2331837-3-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: at_xdmac: call at_xdmac_axi_config() on resume pathClaudiu Beznea
at_xdmac could be used on SoCs which supports backup mode (where most of the SoC power, including power to DMA controller, is closed at suspend time). Thus, on resume, the settings which were previously done need to be restored. Do the same for axi configuration. Fixes: f40566f220a1 ("dmaengine: at_xdmac: add AXI priority support and recommended settings") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211007111230.2331837-2-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: Remove redundant initialization of variable errColin Ian King
The variable err is being initialized with a value that is never read, it is being updated later on. The assignment is redundant and can be removed and move the declaration into the local scope. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20211015123447.27560-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: tegra210-adma: Override ADMA FIFO sizeSameer Pujar
ADMAIF FIFO uses a ring buffer and it is divided amongst the available channels. The default FIFO size (in multiples of 16 words) of ADMAIF TX/RX channels is as below: * On Tegra210, channel 1 to 2 : size = 3 channel 3 to 10: size = 2 * On Tegra186 and later, channel 1 to 4 : size = 3 channel 5 to 20: size = 2 As per recommendation from HW, FIFO size of ADMA channel should be same as the corresponding ADMAIF channel it maps to. FIFO corruption is observed if the sizes do not match. We are using the default FIFO sizes for ADMAIF and there is no plan to support any custom values. Thus at runtime, override the ADMA channel FIFO size value depending on the corresponding ADMAIF channel. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/1631722025-19873-4-git-send-email-spujar@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: tegra210-adma: Add description for 'adma_get_burst_config'Sameer Pujar
Trivial change to add description for 'adma_get_burst_config' in chip data structure. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/1631722025-19873-3-git-send-email-spujar@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-18dmaengine: tegra210-adma: Re-order 'has_outstanding_reqs' memberSameer Pujar
The 'has_outstanding_reqs' member description order in structure 'tegra_adma_chip_data' does not match with the corresponding member declaration. The same is true for member assignment in chip data structures declared for Tegra210 and Tegra186. This is a trivial fix to re-order the mentioned member for a better readability. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/1631722025-19873-2-git-send-email-spujar@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: idxd: move out percpu_ref_exit() to ensure it's outside submissionDave Jiang
percpu_ref_tryget_live() is safe to call as long as ref is between init and exit according to the function comment. Move percpu_ref_exit() so it is called after the dma channel is no longer valid to ensure this holds true. Fixes: 93a40a6d7428 ("dmaengine: idxd: add percpu_ref to descriptor submission path") Suggested-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/163294293832.914350.10326422026738506152.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: stm32-mdma: Use struct_size() helper in devm_kzalloc()Gustavo A. R. Silva
Make use of the struct_size() helper instead of an open-coded version, in order to avoid any potential type mistakes or integer overflows that, in the worse scenario, could lead to heap overflows. Link: https://github.com/KSPP/linux/issues/160 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210929222922.GA357509@embeddedor Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: fix lockdep warning in taskletMichael Tretter
The tasklet that handles the completed dma transfers uses spin_unlock for unlocking a spin lock that was previously locked with spin_lock_irqsave. This caused the following lockdep warning about an inconsistent lock state: inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage. We must use spin_lock_irqsave, because it is possible to queue DMA transfers from an irq handler. Replace the spin_unlock and spin_lock by spin_unlock_irqrestore and spin_lock_irqsave. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-8-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: refine dma descriptor lockingMichael Tretter
The descriptor lists are locked for the entire tasklet that completes the descriptors. This is not necessary, because the lock actually only protects the descriptor lists. Make the spin lock more fine-grained and only protect functions that actually operate on the descriptor lists. This decreases the time when the lock is held. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-7-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: cleanup after completing all descriptorsMichael Tretter
The current implementation iterates the entire done list for each completed dma descriptor even if there are multiple completed descriptors. Avoid this by first moving all completed descriptors to the done list and afterwards iterating the done list and finishing the descriptors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-6-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: cleanup includesMichael Tretter
The driver includes a few headers that are not actually used, but are probably copy paste errors. Remove them. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-5-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: enable COMPILE_TESTMichael Tretter
The driver doesn't use anything architecture specific. Allow the compilation on other architectures as well. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-4-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: drop message on probe successMichael Tretter
There is no need to print a message that the ZynqMP DMA driver probed successfully, since it carries no additional information. Drop the message. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-3-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-10-01dmaengine: zynqmp_dma: simplify with dev_err_probeMichael Tretter
The clocks are provided by the ZynqMP firmware driver and are deferred until the firmware driver has probed. This leads to misleading error messages during probe of the zynqmp_dma driver. Use dev_err_probe for printing errors during probe to avoid error messages for -EPROBE_DEFER. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-2-m.tretter@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-09-09Merge tag 'dmaengine-5.15-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "New drivers/devices - Support for Renesas RZ/G2L dma controller - New driver for AMD PTDMA controller Updates: - Big pile of idxd updates - Updates for Altera driver, stm32-dma, dw etc" * tag 'dmaengine-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (83 commits) dmaengine: sh: fix some NULL dereferences dmaengine: sh: Fix unused initialization of pointer lmdesc MAINTAINERS: Fix AMD PTDMA DRIVER entry dmaengine: ptdma: remove PT_OFFSET to avoid redefnition dmaengine: ptdma: Add debugfs entries for PTDMA dmaengine: ptdma: register PTDMA controller as a DMA resource dmaengine: ptdma: Initial driver for the AMD PTDMA dmaengine: fsl-dpaa2-qdma: Fix spelling mistake "faile" -> "failed" dmaengine: idxd: remove interrupt disable for dev_lock dmaengine: idxd: remove interrupt disable for cmd_lock dmaengine: idxd: fix setting up priv mode for dwq dmaengine: xilinx_dma: Set DMA mask for coherent APIs dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX dmaengine: sh: Add DMAC driver for RZ/G2L SoC dmaengine: Extend the dma_slave_width for 128 bytes dt-bindings: dma: Document RZ/G2L bindings dmaengine: ioat: depends on !UML dmaengine: idxd: set descriptor allocation size to threshold for swq dmaengine: idxd: make submit failure path consistent on desc freeing dmaengine: idxd: remove interrupt flag for completion list spinlock ...
2021-09-01Merge tag 'drivers-5.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "These are updates for drivers that are tied to a particular SoC, including the correspondig device tree bindings: - A couple of reset controller changes for unisoc, uniphier, renesas and zte platforms - memory controller driver fixes for omap and tegra - Rockchip io domain driver updates - Lots of updates for qualcomm platforms, mostly touching their firmware and power management drivers - Tegra FUSE and firmware driver updateѕ - Support for virtio transports in the SCMI firmware framework - cleanup of ixp4xx drivers, towards enabling multiplatform support and bringing it up to date with modern platforms - Minor updates for keystone, mediatek, omap, renesas" * tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits) reset: simple: remove ZTE details in Kconfig help soc: rockchip: io-domain: Remove unneeded semicolon soc: rockchip: io-domain: add rk3568 support dt-bindings: power: add rk3568-pmu-io-domain support bus: ixp4xx: return on error in ixp4xx_exp_probe() soc: renesas: Prefer memcpy() over strcpy() firmware: tegra: Stop using seq_get_buf() soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h> dt-bindings: soc: ti: pruss: Add dma-coherent property soc: ti: Remove pm_runtime_irq_safe() usage for smartreflex soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM64x SoCs dt-bindings: soc: ti: pruss: Update bindings for K3 AM64x SoCs firmware: arm_scmi: Use WARN_ON() to check configured transports firmware: arm_scmi: Fix boolconv.cocci warnings soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing soc: mediatek: mmsys: add MT8365 support ...
2021-08-31dmaengine: sh: fix some NULL dereferencesDan Carpenter
The dma_free_coherent() function needs a valid device pointer or it will crash. Fixes: 550c591a89a1 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20210827085410.GA9183@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-31dmaengine: sh: Fix unused initialization of pointer lmdescColin Ian King
Pointer lmdesc is being inintialized with a value that is never read, it is later being re-assigned a new value. Fix this by initializing it with the latter value. Addresses-Coverity: ("Unused value") Fixes: 550c591a89a1 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210829152811.529766-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: ptdma: remove PT_OFFSET to avoid redefnitionSanjay R Mehta
Building on ARCH=um causes a "redefined" warning, so remove this PT_OFFSET macro to avoid the warning. drivers/dma/ptdma/ptdma.h:34: warning: "PT_OFFSET" redefined 34 | #define PT_OFFSET 0x0 | In file included from ./arch/um/include/asm/thread_info.h:17, from ./include/linux/thread_info.h:60, from ./include/asm-generic/preempt.h:5, from ./arch/um/include/generated/asm/preempt.h:1, from ./include/linux/preempt.h:78, from ./include/linux/spinlock.h:55, from ./include/linux/wait.h:9, from ./include/linux/wait_bit.h:8, from ./include/linux/fs.h:6, from ./include/linux/debugfs.h:15, from drivers/dma/ptdma/ptdma-debugfs.c:12: ./arch/x86/um/shared/sysdep/ptrace_user.h:4: note: this is the location of the previous definition 4 | #define PT_OFFSET(r) ((r) * sizeof(long)) Reported-by: kernel test robot <lkp@intel.com> Fixes: 2a99524459ce ("dmaengine: ptdma: Initial driver for the AMD PTDMA") Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/1630178908-54973-1-git-send-email-Sanju.Mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: ptdma: Add debugfs entries for PTDMASanjay R Mehta
Expose data about the configuration and operation of the PTDMA through debugfs entries: device name, capabilities, configuration, statistics. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/1629208559-51964-4-git-send-email-Sanju.Mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: ptdma: register PTDMA controller as a DMA resourceSanjay R Mehta
Register ptdma queue to Linux dmaengine framework as general-purpose DMA channels. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/1629208559-51964-3-git-send-email-Sanju.Mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: ptdma: Initial driver for the AMD PTDMASanjay R Mehta
Add support for AMD PTDMA controller. It performs high-bandwidth memory to memory and IO copy operation. Device commands are managed via a circular queue of 'descriptors', each of which specifies source and destination addresses for copying a single buffer of data. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Link: https://lore.kernel.org/r/1629208559-51964-2-git-send-email-Sanju.Mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: fsl-dpaa2-qdma: Fix spelling mistake "faile" -> "failed"Colin Ian King
There is a spelling mistake in a dev_err error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210826122500.13743-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: idxd: remove interrupt disable for dev_lockDave Jiang
The spinlock is not being used in hard interrupt context. There is no need to disable irq when acquiring the lock. The interrupt thread handler also is not in bottom half context, therefore we can also remove disabling of the bh. Convert all dev_lock acquisition to plain spin_lock() calls. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/162984026772.1939166.11504067782824765879.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: idxd: remove interrupt disable for cmd_lockDave Jiang
The cmd_lock spinlock is not being used in hard interrupt context. There is no need to disable irq when acquiring the lock. Convert all cmd_lock acquisition to plain spin_lock() calls. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/162984027930.1939209.15758413737332339204.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: idxd: fix setting up priv mode for dwqDave Jiang
DSA spec says WQ priv bit is 0 if the Privileged Mode Enable field of the PCI Express PASID capability is 0 and pasid is enabled. Make sure that the WQCFG priv field is set correctly according to usage type. Reject config if setting up kernel WQ type and no support. Also add the correct priv setup for a descriptor. Fixes: 484f910e93b4 ("dmaengine: idxd: fix wq config registers offset programming") Cc: Ramesh Thomas <ramesh.thomas@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/162939084657.903168.14160019185148244596.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: xilinx_dma: Set DMA mask for coherent APIsRadhey Shyam Pandey
The xilinx dma driver uses the consistent allocations, so for correct operation also set the DMA mask for coherent APIs. It fixes the below kernel crash with dmatest client when DMA IP is configured with 64-bit address width and linux is booted from high (>4GB) memory. Call trace: [ 489.531257] dma_alloc_from_pool+0x8c/0x1c0 [ 489.535431] dma_direct_alloc+0x284/0x330 [ 489.539432] dma_alloc_attrs+0x80/0xf0 [ 489.543174] dma_pool_alloc+0x160/0x2c0 [ 489.547003] xilinx_cdma_prep_memcpy+0xa4/0x180 [ 489.551524] dmatest_func+0x3cc/0x114c [ 489.555266] kthread+0x124/0x130 [ 489.558486] ret_from_fork+0x10/0x3c [ 489.562051] ---[ end trace 248625b2d596a90a ]--- Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Harini Katakam <harini.katakam@xilinx.com> Link: https://lore.kernel.org/r/1629363528-30347-1-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: ti: k3-psil-j721e: Add entry for CSI2RXPratyush Yadav
The CSI2RX subsystem on J721E is serviced by UDMA via PSI-L to transfer frames to memory. It can have up to 32 threads per instance. J721E has two instances of the subsystem, so there are 64 threads total. Add them to the endpoint map. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Peter Ujfalusi <peter.ujflausi@gmail.com> Link: https://lore.kernel.org/r/20210819110106.31409-1-p.yadav@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-29dmaengine: sh: Add DMAC driver for RZ/G2L SoCBiju Das
Add DMA Controller driver for RZ/G2L SoC. Based on the work done by Chris Brandt for RZ/A DMA driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210806095322.2326-4-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-25dmaengine: ioat: depends on !UMLJohannes Berg
Now that UML has PCI support, this driver must depend also on !UML since it pokes at X86_64 architecture internals that don't exist on ARCH=um. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20210809112409.a3a0974874d2.I2ffe3d11ed37f735da2f39884a74c953b258b995@changeid Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-25dmaengine: idxd: set descriptor allocation size to threshold for swqDave Jiang
Since submission is sent to limited portal, the actual wq size for shared wq is set by the threshold rather than the wq size. When the wq type is shared, set the allocated descriptors to the threshold. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/162827151733.3459223.3829837172226042408.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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