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2026-05-11drm/amd/display: Introduce FRL registers for DCN32Rodrigo Siqueira
This commit add the basic set of FRL registers associated with DCN32. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN321Rodrigo Siqueira
Add the required DCN3.2.1 registers to enable FRL in this ASIC. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add required FRL registers for DCN31Rodrigo Siqueira
This commit introduces multiple hardware registers necessary to enable FRL on AMD devices. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN30Rodrigo Siqueira
Introduce the stream creation function, which requires the FRL registers for DCN30. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/ras: Fix CPER ring debugfs read overflowXiang Liu
The legacy CPER debugfs reader can reach the payload path without a valid pointer snapshot. The remaining user byte count is also treated as the ring occupancy in dwords, so reads past the header can copy more than requested. Take the CPER lock before sampling pointers. Resample rptr/wptr for payload reads, bound the payload copy by available dwords and the remaining user size, and advance the file position for each dword copied. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: Sync the pf2vf structure between guest and hostchong li
There are gaps in the pf2vf message structure between the guest driver and the host driver. The pf2vf message info structure must be kept in sync between both sides to ensure correct interpretation of fields. Signed-off-by: chong li <chongli2@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Promote DC to 3.2.382Taimur Hassan
This version brings along following update: -Revert "Enable HUBP/OPTC/DPP power gating" -Revert "Unify fast update classification paths" -enable ODM 2:1 on single eDP based on pixel clock -Enable IPS on DCN42 -Add additional IPS entry/exit for PSR/Replay -Separate ABM functions into dedicated power_abm.c file -Fix always-true lower-bound assert -Refactor dc_link_aux_transfer_raw -only call pmfw if smu present flags true -Fix multiple compiler warnings -Fix CRC open failure during active rendering -Fix white screen on boot with OLED panel -Fix refresh rate round up case Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: [FW Promotion] Release 0.1.59.0Taimur Hassan
[Why & How] Update DMUB related command structure. Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Wrap DCN32 phantom-plane allocation in ↵Mikhail Gavrilov
DC_RUN_WITH_PREEMPTION_ENABLED [Why] dcn32_validate_bandwidth() wraps dcn32_internal_validate_bw() with DC_FP_START()/DC_FP_END(). In x86 non-RT, DC_FP_START takes fpregs_lock(), which disables local softirqs. The DML1 path through dcn32_enable_phantom_plane() calls kvzalloc() to allocate ~335 KiB for dc_plane_state. This triggers the vmalloc path, which calls BUG_ON(in_interrupt()) because it's invoked within the FPU-enabled (softirq disabled) region, leading to a kernel crash. [How] Wrap the dc_state_create_phantom_plane() call with the DC_RUN_WITH_PREEMPTION_ENABLED() macro to allow preemption during this memory allocation. Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4470 Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating"Leo Chen
[why & how] Pipe power gating is causing regressions. Revert to unblock testing and promotion This reverts commit 2eb0681ea7604880ade2d715e4212132c393c132. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Revert "Unify fast update classification paths"Ovidiu Bunea
[why & how] This change causes regressions in ACPI and display off/on testing. Revert the change to unblock testing. This reverts commit 5f6937c1afb151c85af721fad180d588060430d7. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: enable ODM 2:1 on single eDP based on pixel clockCharlene Liu
[Why & How] this is to force ODM 2:1 on single eDP to lower dispclk/dppclk. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix enum decl warningsGaghik Khachatrian
[Why] warnings were triggered by enum forward declarations that are not valid in C++ without an explicit underlying type. [How] - Replace problematic enum forward declarations with C++-safe forms where applicable. - Use plain integer types for interface-only declarations that do not require strong enum typing. - Update dependent winterface signatures and related type usage consistently. - Add required include and type-visibility fixes to avoid follow-on parse and type-resolution issues. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Enable IPS on DCN42Ivan Lipski
[Why & How] Fully enable IPS to achieve higher power savings. Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add additional IPS entry/exit for PSR/ReplayIvan Lipski
[Why] Multiple paths issue DMUB commands without managing IPS state, causing dc_wake_and_execute_gpint/dmub_cmd to internally wake from IPS and reallow idle. This flips idle_allowed back to true while idle_optimizations_allowed remains false during in-flight commits, desynchronizing the two flags. Affected paths: - amdgpu_dm_psr_set_event() and amdgpu_dm_replay_set_event() calls from amdgpu_dm_handle_vrr_transition(), amdgpu_dm_commit_planes() and amdgpu_dm_mod_power_update_streams(), that are invoked on atomic commits. - debugfs psr_get(), psr_read_residency(), replay_get_state(), replay_set_residency() access hardware without holding dc_lock or disabling IPS. [How] - Explicitly exit IPS before PSR/Replay set_event w/ hw_programming, called within atomic commit. - Wrap debugfs PSR/Replay state getters and setters with IPS exit/entry + dc_lock. Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Separate ABM functions into dedicated power_abm.c fileLohita Mudimela
[Why] Improves code organization by separating Adaptive Backlight Modulation functionality from general power management. This modular approach enhances maintainability and makes the codebase easier to navigate. [How] Create new power_abm.c file containing all ABM-related functions moved from power.c. Remove static qualifier from shared functions to enable cross-file access: - initialize_backlight_caps: Initialize backlight capabilities - validate_ext_backlight_caps: Validate external backlight capabilities - backlight_millipercent_to_pwm: Convert brightness percent to PWM - backlight_millipercent_to_millinit: Convert brightness percent to nits - fill_backlight_level_params: Populate backlight level parametersAdd function declarations to mod_power.h header. Update CMakeLists.txt to include power_abm.c in build. Maintain forward declaration of struct core_power for type compatibility. Rename struct core_power field from 'public' to 'mod_public'. Move internal structures (backlight_state, backlight_properties, dmcu_varibright_cached_properties, core_power) to power_helpers.h to ensure consistent memory layouts across compilation units. Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Lohita Mudimela <lohita.mudimela@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: always-true lower-bound assertGaghik Khachatrian
[Why] A recent type change made the lower-bound part of the OTG instance assert redundant, which can trigger static-analysis noise and distract from actionable diagnostics. [How] Kept the meaningful upper-bound range validation required for safe narrowing to uint8_t. Removed the redundant non-negative portion of the assert so the check matches current type semantics. Revalidated with the latest debug build log: no warnings and no build-failure markers. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Introduce dc_plane_cm and migrate surface update color pathRafal Ostrowski
[Why] Introduce dc_plane_cm struct. TRIM_CM2 flag is used to synchronize between old and new implementation. [How] Introduce dc_plane_cm struct. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Refactor dc_link_aux_transfer_rawMatthew Stewart
[Why & How] The logic for choosing between the dce_aux_transfer function variants is moved into dce_aux.c rather than link_ddc.c. The "dce_aux_transfer_with_retries" function now uses dce_aux_transfer_raw in its implementation as the logic is equivalent. Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Reviewed-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: only call pmfw if smu present flags trueCharlene Liu
[Why & How] for fault safe case: only call pmfw if smu present flags true and default to 2 channle for bios intergration info table error. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix warningsClay King
[Why & How] Fix various warnings related to unsigned/signed mismatches - Consistently use the same signedness for a given value - Explcitly cast between types when needed Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix multiple compiler warningsGaghik Khachatrian
[Why] Unreachable Code; Copy Constructor Deleted; Local Declaration Hides Parameter; Local Declaration Hides Outer Scope; Uninitialized or Suspicious Memory Use. [How] - Removed or refactored unreachable code paths - Ensured proper copy constructors in C++ classes - Renamed local variables that shadowed function parameters - Renamed inner loop/block variables to avoid shadowing outer scope Fixed in 8 files across several FPU layers Also fixed in color_gamma and cs_funcs modules - Reordered guard conditions to validate pipe type before accessing stream - Ensures safe memory access patterns in DC DMUB service layer All changes maintain backward compatibility and preserve functional behavior. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix compiler warnings in dml2Gaghik Khachatrian
[Why & How] In dml2_translation_helper.c, rename the inner loop index inside dml2_init_soc_states() for several project cases to avoid shadowing the outer function-scope index variable. In display_mode_core.c, replace shift-based power-of-two expressions used to compute dpte_row_height and dpte_row_height_linear with an equivalent floating-point power function, consistent with existing usage elsewhere in the file. Behavior for valid inputs is preserved in both cases. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix signed/unsigned comparison mismatchesGaghik Khachatrian
[Why] Address signed/unsigned comparison warnings in DC paths to keep builds warning-clean and improve type safety at comparison boundaries. Most warnings came from signed loop/index temporaries compared against unsigned counters (for example pipe_count, num_states, and resource-cap counters), plus a small number of mixed signed/unsigned checks in writeback and clock-related assertions. [How] Aligned iterator and temporary variable types with the semantic type of the compared bounds. Used unsigned indices for loops bounded by unsigned counters, and retained signed types where values are semantically signed (for example arithmetic with sentinel or signed intermediate values). Where mixed signed/unsigned comparisons are intentional, applied explicit boundary casts or split assertions (for example non-negative signed-cap checks before unsigned comparisons) instead of broad type changes. No functional behavior changes are intended; this is a warning-resolution and type-alignment cleanup. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix CRC open failure during active renderingTom Chung
[Why] Opening the CRC data file during active rendering can fail with -EINVAL. The wait for commit->hw_done returns remaining jiffies on success, but the CRC path was treating that as an error. [How] Handle wait_for_completion_interruptible_timeout() correctly: positive return as success, 0 as timeout, and negative as error. Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix white screen on boot with OLED panelRay Wu
[Why] During mode change, replay_event_general_ui may remain set on the old stream while replay_event_hw_programming is set. This can re-enable Replay too early before hardware programming is complete. [How] Clear replay_event_general_ui in the mode-change path when setting replay_event_hw_programming to keep Replay blocked until programming finishes, avoiding white screen on OLED panels after boot. Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Fix refresh rate round up caseChunTao Tso
[Why & How] fix refresh rate round up case Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: fix error return code in mes_v12_1_map_test_boYang Wang
The function mes_v12_1_map_test_bo incorrectly returned 0 unconditionallyon error path, which would hide the real error code and mislead upperlayers about the failure status. Fix it by returning the correct error code 'r' instead of 0. Fixes: 44e5195fa3d4 ("drm/amdgpu/mes_v12_1: add mes self test"); Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0_8Yang Wang
Convert the SMU15.0.8 enabled-feature query to smu_cmn_send_smc_msg_with_params() so it uses the common SMU multi-msgs helper. No functional change intended. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0_0Yang Wang
Convert the SMU15.0.0 table transfer path and enabled-feature query to smu_cmn_send_smc_msg_with_params() so both paths use the common SMU multi-msgs helper. No functional change intended. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: fix userq hang detection and resetChristian König
Fix lock inversions pointed out by Prike and Sunil. The hang detection timeout *CAN'T* grab locks under which we wait for fences, especially not the userq_mutex lock. Then instead of this completely broken handling with the hang_detect_fence just cancel the work when fences are processed and re-start if necessary. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: remove almost all calls to amdgpu_userq_detect_and_reset_queuesChristian König
Well the reset handling seems broken on multiple levels. As first step of fixing this remove most calls to the hang detection. That function should only be called after we run into a timeout! And *NOT* as random check spread over the code in multiple places. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: rework amdgpu_userq_signal_ioctl v3Christian König
This one was fortunately not looking so bad as the wait ioctl path, but there were still a few things which could be fixed/improved: 1. Allocating with GFP_ATOMIC was quite unnecessary, we can do that before taking the userq_lock. 2. Use a new mutex as protection for the fence_drv_xa so that we can do memory allocations while holding it. 3. Starting the reset timer is unnecessary when the fence is already signaled when we create it. 4. Cleanup error handling, avoid trying to free the queue when we don't even got one. v2: fix incorrect usage of xa_find, destroy the new mutex on error v3: cleanup ref ordering Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0Yang Wang
Convert the SMU15 table address messages to smu_cmn_send_smc_msg_with_params() so they use the common SMU multi-msgs helper instead of open-coding struct smu_msg_args. No functional change intended. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/pm: add SMU multi-msgs helpersYang Wang
SMU15 driver messages can carry multiple input parameters and return values, but callers still have to build struct smu_msg_args directly. Add common SMU multi-msgs helpers in smu_cmn and reuse them in the single-parameter wrapper and the shared table transfer path. Keep smu_cmn_send_smc_msg() semantics unchanged for older callers. No functional change intended. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: remove deadlocks from amdgpu_userq_pre_resetChristian König
The purpose of a GPU reset is to make sure that fence can be signaled again and the signal and resume workers can make progress again. So waiting for the resume worker or any fence in the GPU reset path is just utterly nonsense. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: fix ptl state isssue after GPU reset or suspendPerry Yuan
Fix this by skipping the sysfs disable mapping when the GPU is currently undergoing a reset or suspend flow. Additionally, add debug logging in psp_ptl_invoke() to better trace PTL state and format queries/updates cmd. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu/gfx9.4.3: skip PTL disable during GPU resetPerry Yuan
During RAS UE-triggered GPU reset, gfx_v9_4_3_hw_fini() attempts to send a PTL disable command to PSP. Since PSP is unresponsive at that point, this produces spurious error logs on all hive nodes: PTL command 0xa0000001 failed, PSP response status: 0xFFFFFFFF PTL initialization failed (-5) Skip the PTL disable command when GPU reset is in progress, as PTL will be properly re-initialized during post-reset recovery via gfx_v9_4_3_late_init(). Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: only set PTL SYSFS disable bit when PTL is disabledPerry Yuan
Only set the bit when PTL is actually being disabled (state=0) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdkfd: fix unhalt_cpsch warning during module unloadPerry Yuan
Downgrade unhalt_cpsch warning to dev_dbg when sched is already stopped Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: create PTL sysfs after XGMI reset-on-init restorePerry Yuan
Create PTL sysfs in xgmi_reset_on_init restore path for MINIMAL_XGMI Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: Move KFD sched stop/start into PTL control pathPerry Yuan
Move amdgpu_amdkfd_stop/start_sched calls from kfd_ptl_control() into amdgpu_ptl_perf_monitor_ctrl() so all PTL callers (KFD ioctl, sysfs, GFX init) get consistent scheduling management. Add amdgpu_amdkfd_stop/start_sched_all() wrappers to stop and restart KFD scheduling on all nodes without assuming node ID ordering. v3: * call start/stop for PTL Set Only v2: * move the stop/start sched function to amdgpu_ptl_perf_monitor_ctrl(Lijo) * add wrapper amdgpu_amdkfd_stop_sched_all and amdgpu_amdkfd_start_sched_all (Lijo) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: add SPI idle check for GC 9.4.4 in gfx_v9_4_3_is_idle()Perry Yuan
GC 9.4.4 uses SPI busy status for idle detection instead of GRBM GUI_ACTIVE. Add version check to use SPI_BUSY for 9.4.4 while keeping GRBM_STATUS GUI_ACTIVE check for other GC versions. v2: move this check into amdgpu_ptl_perf_monitor_ctrl(Lijo) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: check PSP response status in psp_ptl_invokePerry Yuan
Add an explicit check on cmd->resp.status after psp_cmd_submit_buf() returns to ensure PTL state is only updated on actual success. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: Wait for GFX idle before PTL state transitionPerry Yuan
Ensure GFX engine is idle before switching PTL state to prevent register access violations and CP hang. This addresses the race condition where in-flight GPU commands could conflict with PTL state changes. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: add new data types F8 and Vector for PTLPerry Yuan
Add F8 and VECTOR to amdgpu_ptl_fmt and PSP format mapping. Update PTL format strings and GFX format enum to keep PSP/KFD in sync. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: add amdgpu.ptl module parameter for PTL controlPerry Yuan
Add a new kernel module parameter 'amdgpu.ptl' to allow users to enable or disable PTL feature at driver loading time. Parameter values: *) 0 or -1: disable PTL (default) *) 1: enable PTL *) 2: permanently disable PTL Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu: Track PTL disable requests by sourcePerry Yuan
Use a bitmap to track PTL disable requests from sysfs and profiler. PTL is only re-enabled once all sources have released their disable requests, avoiding premature enablement. Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdkfd: suspend scheduler during PTL re-enablingPerry Yuan
Stop the scheduler before releasing the PTL disable request to ensure the GPU is quiescent during the PTL state transition. This prevents potential queue preemption failures and GPU resets caused by modifying PTL state while waves are executing v1->v2: only stop/start the scheduler when the PTL state actually needs to transition(Yifan) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdkfd: Add PTL control IOCTL Option and unify refcount logicPerry Yuan
Introduce a new IOCTL option to allow userspace explicit control over the Peak Tops Limiter (PTL) state for profiling Link: https://github.com/ROCm/rocm-systems/tree/develop/projects/rocprofiler-sdk Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-17 18:41:52 +0000