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2026-05-05drm/amd/display: Skip HDR metadata update when Smart Power OLED enabledIan Chen
[Why & How] While smart power oled is enabled, the infopacket contents are tied to the frame histogram, so it does not need driver side to update the hdr metadata. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Rename backlight_properties to pwr_backlight_propertiesRay Wu
[Why] 'struct backlight_properties' in power.c has the same name as the kernel's struct defined in <linux/backlight.h>. In out-of-tree backport build environments, the header is forcefully injected via command-line includes, causing a redefinition error. [How] Rename the file-local 'struct backlight_properties' to 'pwr_backlight_properties' to avoid the name collision. No functional change. Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: remove watermark range notifyCharlene Liu
[Why & How] dcn42 only use one set of watermark A, driver always update set A runtime. no need to notify pmfw the clock range. Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Clean Up Legacy DML ContentZheng, Austin
[Why & How] Legacy files were used for the transition period between DML1 and DML2. Fully transitioned away from DML1 so these legacy files can be removed since they are not actively being used. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Zheng Austin <Austin.Zheng@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Implement block sequencing infrastructure for modular ↵Bhuvanachandra Pinninti
hardware operations. [why] Hardware sequencer operations need better modularity and testability. Current monolithic functions make it difficult to unit test individual operations and create maintainable workflows. [how] Implement new hwss_add_* helper functions with standardized parameter structures. Add block_sequence_state framework for execution context management. Create cursor, info frame, DSC, and stream encoder sequence functions with comprehensive unit test support. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Bhuvanachandra Pinninti <BhuvanaChandra.Pinninti@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Do DML float narrowing explicitGaghik Khachatrian
[Why] Shared DML wrapper helpers in [dc/dml/dml_inline_defs.h](dc/dml/dml_inline_defs.h) pass double and int values to float-based dcn_bw_* helpers. Make these intentional narrowing boundaries explicit to reduce warning noise without changing behavior. [How] Add explicit C-style casts at the float API boundary in the shared DML inline wrappers used by the DCN DML paths. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Fix type mismatches in DML and normalize loop boundsGaghik Khachatrian
[Why] Address signed/unsigned comparison warnings across DML paths to keep builds warning-clean and improve type safety at comparison boundaries. Most warnings came from signed loop/index temporaries compared against unsigned counters (for example pipe_count, num_states, and candidate/state counts), plus a small number of mixed signed/unsigned clock and geometry checks. [How] Aligned iterator and temporary variable types with the semantic type of the compared bounds. Used unsigned indices for loops bounded by unsigned counters, and retained signed types where values are semantically signed (for example plane_count math, timing/micro-schedule arithmetic, and reverse/sentinel-style iteration). Where mixed signed/unsigned comparisons are intentional, applied explicit boundary casts instead of broad type changes (for example dispclk minimum clamp and selected timing/height comparisons). As a side effect of converting count parameters such as NumberOfActivePlanes to unsigned, normalized equivalent loop forms from: for (i = 0; i <= NumberOfActivePlanes - 1; i++) into the normalized form: for (i = 0; i < NumberOfActivePlanes; i++) to keep bound style coherent and avoid avoidable mismatch patterns. No functional behavior changes are intended; this is a warning-resolution and type-alignment cleanup. Assisted-by: Copilot Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Remove unused state param from enable_link_analogAlex Hung
[WHY & HOW] The 'state' parameter in enable_link_analog() is never used within the function body. Remove it from the function. Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: Fix Color Manager (3DLUT, Shaper, Blend)Dillon Varone
[WHY & HOW] The original refactor and fixes are causing regressions. Revert them for now until they can be resolved Fixes: e56e3cff2a1b ("drm/amd/display: Sync dcn42 with DC 3.2.373") Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdkfd: remove obsolete codes for kfd_mmapEric Huang
kfd_reserved_mem_mmap is only for mapping CWSR on APU in IOMMUv2 mode, which is no longer supported, and qpd->cwsr_base has been set before calling kfd_process_init_cwsr_apu, which is the only caller for KFD_MMAP_TYPE_RESERVED_MEM, so kfd_process_init_cwsr_apu is not functional anymore, remove them together. On the other hand, it will fix a vulnerability issue to abuse KFD_MMAP_TYPE_RESERVED_MEM of kfd_mmap from userspace. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/pm: Relax manual min/max clock checkAsad Kamal
Allow min == max for the soft frequency limit when AMD_DPM_FORCED_LEVEL_MANUAL is used on SMU v13.0.6 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: Use helper to set gart sizeLijo Lazar
Find the default size required and use the helper funcction to set gart size. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: Add helper to set gart sizeLijo Lazar
Add a helper to make any adjustments to gart size based on other parameters or conditions. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdkfd: Check if there are kfd porcesses using adev by kfd_processes_countXiaogang Chen
During gpu hot-unplug need check if there are kfd porcesses still using the being removed gpu before clean resources of the device. Current driver checks if kfd_processes_table is empty. kfd processes are not terminated after removed from kfd_processes_table immediately. They are still alive and may access the device until kfd_process_wq work queue got ran. Check kfd->kfd_processes_count value that is updated after kfd process got uninitialized when its ref becomes zero. Fixes: 6cca686dfce7 ("drm/amdkfd: kfd driver supports hot unplug/replug amdgpu devices") Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: Prefer ROM BAR for default VGA deviceLijo Lazar
Fetching from platform ROM doesn't work with hybrid ROM images. For default VGA devices also prefer ROM BAR. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: zero-initialize GART table on allocationPhilip Yang
GART TLB is flushed after unmapping but not after mapping. Since amdgpu_bo_create_kernel() does not zero-initialize the buffer, when a single PTE is written the TLB may speculatively load other uninitialized entries from the same cacheline. Those garbage entries can appear valid, and a subsequent write to another PTE in the same cacheline may cause the GPU to use a stale garbage PTE from the TLB. Fix this by calling memset_io() to zero-initialize the GART table with gart_pte_flags immediately after allocation. Using AMDGPU_GEM_CREATE_VRAM_CLEARED, SDMA-based clear will not work since SDMA needs GART to be initialized to work. Suggested-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu/sdma4: replace BUG_ON with WARN_ON in fence emissionJohn B. Moore
sdma_v4_0_ring_emit_fence() contains two BUG_ON(addr & 0x3) assertions that verify fence writeback addresses are dword-aligned. These assertions can be reached from unprivileged userspace via crafted DRM_IOCTL_AMDGPU_CS submissions, causing a fatal kernel panic in a scheduler worker thread. Replace both BUG_ON() calls with WARN_ON() to log the condition without crashing the kernel. A misaligned fence address at this point indicates a driver bug, but crashing the kernel is never the correct response when the assertion is reachable from userspace. The CS IOCTL path is the correct place to filter invalid submissions; the ring emission callback is too late to do anything about it. Fixes: 2130f89ced2c ("drm/amdgpu: add SDMA v4.0 implementation (v2)") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: John B. Moore <jbmoore61@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/radeon: add missing revision check for CIAlex Deucher
The memory level workarounds only apply to revision 0 SKUs. Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816 Fixes: 127e056e2a82 ("drm/radeon: fix mclk vddc configuration for cards for hawaii") Fixes: 21b8a369046f ("drm/radeon: fix dram timing for certain hawaii boards") Fixes: 90b2fee35cb9 ("drm/radeon: fix dpm mc init for certain hawaii boards") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu/pm: align Hawaii mclk workaround with radeonAlex Deucher
Align the hawaii mclk workaround with radeon and windows. Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816 Fixes: 9f4b35411cfe ("drm/amd/powerplay: add CI asics support to smumgr (v3)") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu/pm: add missing revision check for CIAlex Deucher
The ci_populate_all_memory_levels() workaround only applies to revision 0 SKUs. Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816 Fixes: 9f4b35411cfe ("drm/amd/powerplay: add CI asics support to smumgr (v3)") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu/gfx9: drop unnecessary 64-bit fence flag check in KIQJohn B. Moore
Remove the BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT) assertion from gfx_v9_0_ring_emit_fence_kiq(). The KIQ hardware supports 64-bit fence writes; the 32-bit writeback address constraint is an upper-layer convention, not a hardware limitation. The check serves no purpose and should not be present. Found by code inspection while investigating related BUG_ON assertions in the GFX and compute ring emission paths. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: John B. Moore <jbmoore61@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: deduplicate ring preempt ib functionLeonardo Cesar
The ring preemption function is identical for both gfx_v11_0 and gfx_v12_0. This patch refactors the code by moving the core logic into a generic function inside amdgpu_gfx.c to reduce code duplication and simplify future maintenance. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leonardo Cesar <leonardocesar@usp.br> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdkfd: Make all TLB-flushes heavy-weightFelix Kuehling
With only one sequence number we cannot track the need for legacy vs heavy-weight flushes reliably. Always use heavy-weight. Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amdgpu: amdgpu{_reset}.h: fix all kernel-doc warningsRandy Dunlap
Fix all kernel-doc warnings in amdgpu.h and amdgpu_reset.h: - Use the struct keyword for kernel-doc struct comments. - Use the correct enum names in enum amd_reset_method. This eliminates these warnings: Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:477 cannot understand function prototype: 'struct amdgpu_wb' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_LEGACY' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_MODE0' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_MODE1' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_MODE2' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_LINK' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_BACO' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_PCI' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Enum value 'AMD_RESET_METHOD_ON_INIT' not described in enum 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_LEGACY' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_MODE0' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_MODE1' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_MODE2' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_LINK' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_BACO' description in 'amd_reset_method' Warning: drivers/gpu/drm/amd/amdgpu/amdgpu.h:576 Excess enum value '@AMD_RESET_PCI' description in 'amd_reset_method' Also move the enum to amdgpu_reset.h and eventually only forward declare it in amdgpu.h. (Christian) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: dmub_cmd.h: add missing kernel-doc for enumsRandy Dunlap
For enums that have a kernel-doc ("/**") comment block, add or correct their kernel-doc to eliminate all kernel-doc enum warnings. Some of these needed "struct" changed to "enum" in the kernel-doc header. For a few of them, I changed the "/**" comment to a plain "/*" comment since there was no kernel-doc content there. Example: Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2673 Enum value 'FAMS2_ALLOW_DELAY_CHECK_NONE' not described in enum 'dmub_fams2_allow_delay_check_mode' Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2673 Enum value 'FAMS2_ALLOW_DELAY_CHECK_FROM_START' not described in enum 'dmub_fams2_allow_delay_check_mode' Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2673 Enum value 'FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE' not described in enum 'dmub_fams2_allow_delay_check_mode' All .o files are the same with or without this patch. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: dmub_cmd.h: correct all kernel-doc prototype warningsRandy Dunlap
Correct all typedef, struct, and union prototype warnings in dmub_cmd.h by using the matching names or "typedef" keyword: Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:961 cannot understand function prototype: 'typedef uint32_t dmub_trace_code_t;' Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:1183 expecting prototype for union dmub_shared_state_ips_fw. Prototype was for union dmub_shared_state_ips_fw_signals instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:1203 expecting prototype for union dmub_shared_state_ips_signals. Prototype was for union dmub_shared_state_ips_driver_signals instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:1253 expecting prototype for struct dmub_shared_state_cursor_offload_v1. Prototype was for struct dmub_shared_state_cursor_offload_stream_v1 instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:1269 struct dmub_shared _state_feature_common { uint32_t padding[62]; };: error: Cannot parse enum! Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:1278 struct dmub_shared _state_feature_header { uint16_t id; uint16_t version; uint32_t reserved; };: error: Cannot parse enum! Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2001 expecting prototype for struct dmub_cmd_read_modify_write_sequence. Prototype was for struct dmub_rb_cmd_read_modify_write instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2191 expecting prototype for struct dmub_rb_cmd_cab. Prototype was for struct dmub_rb_cmd_cab_for_ss instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:2875 expecting prototype for struct dmub_cmd_set_pixel_clock_data. Prototype was for struct dmub_rb_cmd_set_pixel_clock instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:3398 expecting prototype for union dpia_notify_data_type. Prototype was for union dpia_notification_data instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:3447 expecting prototype for struct dmub_rb_cmd_hpd_sense_notify. Prototype was for struct dmub_rb_cmd_hpd_sense_notify_data instead Warning: drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h:6267 expecting prototype for struct dmub_cmd_cable_id_input. Prototype was for struct dmub_cmd_cable_id_output instead Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/amd/display: dmub_cmd.h: correct typos and spellosRandy Dunlap
Fix spelling issues that are reported by codespell: dmub_cmd.h:332: alighment ==> alignment dmub_cmd.h:2029: sequeunce ==> sequence dmub_cmd.h:3684: optimzations ==> optimizations dmub_cmd.h:4491: isntance ==> instance dmub_cmd.h:4514: optimzations ==> optimizations dmub_cmd.h:4604: isntance ==> instance dmub_cmd.h:4643: isntance ==> instance dmub_cmd.h:4679: isntance ==> instance dmub_cmd.h:4699: isntance ==> instance dmub_cmd.h:4719: isntance ==> instance dmub_cmd.h:4735: isntance ==> instance dmub_cmd.h:4749: isntance ==> instance dmub_cmd.h:4795: isntance ==> instance dmub_cmd.h:4903: isntance ==> instance dmub_cmd.h:4936: isntance ==> instance dmub_cmd.h:5066: re-use ==> reuse dmub_cmd.h:6552: isntance ==> instance dmub_cmd.h:6630: isntance ==> instance dmub_cmd.h:6639: optimzations ==> optimizations dmub_cmd.h:6720: isntance ==> instance dmub_cmd.h:6742: isntance ==> instance and fix a few that I found: dicated ==> dictated (7x) afftet ==> after (is this correct?) Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-05drm/i915: replace select with dependency for visible DEBUG_OBJECTSJulian Braha
DRM_I915_SW_FENCE_DEBUG_OBJECTS currently selects DEBUG_OBJECTS even though DEBUG_OBJECTS is visible to users. Other config options use 'depends on' for DEBUG_OBJECTS, so let's do the same here. This select-visible Kconfig misusage was detected by Kconfirm, a static analysis tool for Kconfig. Signed-off-by: Julian Braha <julianbraha@gmail.com> Link: https://patch.msgid.link/20260502191932.4491-1-julianbraha@gmail.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-05drm/panel: jadard-jd9365da-h3: Fix signedness bugEthan Tidmore
The function drm_of_get_data_lanes_count_remote() returns negative error codes and dsi->lanes is an unsigned integer, so the check (dsi->lanes < 0) is always impossible. Detected by Smatch: drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c:2959 jadard_dsi_probe() warn: unsigned 'dsi->lanes' is never less than zero. Fixes: eb019688f2a97 ("drm/panel: jadard-jd9365da-h3: support variable DSI configuration") Signed-off-by: Ethan Tidmore <ethantidmore06@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260429024954.697411-1-ethantidmore06@gmail.com
2026-05-05drm/panel: focaltech-ota7290b: Fix error check for devm_drm_panel_alloc()Chen Ni
The devm_drm_panel_alloc() function returns an error pointer on failure, not NULL. Fix the check to use IS_ERR() and return PTR_ERR() to correctly handle allocation failures. Fixes: 07853e954248 ("drm/panel: add driver for Waveshare 8.8" DSI TOUCH-A panel") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260429080527.1456732-1-nichen@iscas.ac.cn
2026-05-05drm/panel: himax-hx83102: restore MODE_LPM after sending disable cmdsIcenowy Zheng
When preparing the panel, it seems that it always expects commands to be transferred in LP mode. However, the disable function removes the MIPI_DSI_MODE_LPM flag, and no other function re-adds it. As the unprepare function contains no DSI commands, re-adding the flag just after disabling the panel should be safe. Add the code re-adding the flag after the two commands for disabling the panel are sent. This fixes screen unblanking (after blanking once) on mt8188-geralt-ciri-sku1 device. Cc: stable@vger.kernel.org # 6.11+ Fixes: 0ef94554dc40 ("drm/panel: himax-hx83102: Break out as separate driver") Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260425165751.1716569-1-zhengxingda@iscas.ac.cn
2026-05-05drm/panel: boe-tv101wum-nl6: restore MODE_LPM after sending disable cmdsIcenowy Zheng
When preparing the panel, it seems that it always expects commands to be transferred in LP mode. However, the disable function removes the MIPI_DSI_MODE_LPM flag, and no other function re-adds it. As the unprepare function contains no DSI commands, re-adding the flag just after disabling the panel should be safe. Add the code re-adding the flag after the two commands for disabling the panel are sent. This fixes error messages shown in kernel log when unblanking on mt8183-kukui-kodama-sku32 device. Cc: stable@vger.kernel.org Fixes: a869b9db7adf ("drm/panel: support for boe tv101wum-nl6 wuxga dsi video mode panel") Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260503091708.1079962-1-zhengxingda@iscas.ac.cn
2026-05-05drm/panel: feiyang-fy07024di26a30d: return display-on errorChristian Van
mipi_dsi_dcs_set_display_on() returns an error code, but feiyang_enable() currently ignores it and always reports success. Return the DCS command result so callers can observe enable failures. Signed-off-by: Christian Van <cvan20191@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260425053948.117714-1-cvan20191@gmail.com
2026-05-05drm/panel: hx83121a: select DRM_DISPLAY_DSC_HELPERArnd Bergmann
Like a number of other panel drivers, this newly merged driver needs DRM_DISPLAY_DSC_HELPER to be enabled: arm-linux-gnueabi-ld: drivers/gpu/drm/panel/panel-himax-hx83121a.o: in function `himax_prepare': panel-himax-hx83121a.c:(.text+0x1024): undefined reference to `drm_dsc_pps_payload_pack' Fixes: a7c61963b727 ("drm/panel: Add Himax HX83121A panel driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: David Heidelberg <david@ixit.cz> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260413071043.3829868-1-arnd@kernel.org
2026-05-05drm/panel: himax-hx83121a: Fix incorrect error check for devm_drm_panel_alloc()Chen Ni
Check devm_drm_panel_alloc() return value for ERR_PTR instead of NULL. devm_drm_panel_alloc() returns an ERR_PTR on failure, never NULL. Using a NULL check skips the error path and may cause a NULL pointer dereference. Fixes: a7c61963b727 ("drm/panel: Add Himax HX83121A panel driver") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Reviewed-by: Pengyu Luo <mitltlatltl@gmail.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260327021728.647182-1-nichen@iscas.ac.cn
2026-05-05drm/i915: remove HAS_PCH_NOP() dependency from clock gatingLuca Coelho
intel_pch_init_clock_gating() already handles unsupported PCH types, including PCH_NOP, by doing nothing. Drop the explicit HAS_PCH_NOP() check from the IVB clock gating path and always call the display helper directly. This removes one more direct dependency on display-side PCH macros from intel_clock_gating.c. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-9-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915/display: move pre-HSW clock gating init to displayLuca Coelho
Move the remaining pre-HSW display clock gating programming into display. This also drops display register includes from intel_clock_gating.c. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-8-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915/display: move HSW and BDW clock gating init to displayLuca Coelho
Move the HSW and BDW display clock gating programming into the display code. In this case we need two different helpers, because the common code between these two is split in the middle. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-7-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915/display: move GLK clock gating init to displayLuca Coelho
Move the GLK-specific display clock gating programming into display intel_display_clock_gating.c, to remove more dependencies from i915 to display registers. Now that all remaining Gen9-family callers moved into display, we can move the shared Gen9 display clock gating helper into display and remove the old local helper from intel_clock_gating.c. Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was protected by HAS_LLC(), but that's incidental, because in Gen9 platforms, only SKL and KBL, for which this workaround applies, have LLC(). In order not to use HAS_LLC() in display code, we can simply remove this check from the generic Gen9 function and move the SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific functions. And, intentionally or not, CFL and CML were also using this workaround, because they also have LLC, even though the comments were only mentioning SKL and KBL. In order not to change anything functionally with this patch, the workaround was also added to intel_display_cfl_init_clock_gating(). Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-6-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915/display: move BXT clock gating init to displayLuca Coelho
Move the BXT-specific display clock gating programming into display intel_display_clock_gating.c, to remove more dependencies from i915. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-5-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915/display: move CFL clock gating init to displayLuca Coelho
Move the CFL/CML-specific display clock gating programming into display intel_display_clock_gating.c, to remove more dependencies from i915 to display registers. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-4-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915: move KBL clock gating init to displayLuca Coelho
Move the KBL-specific display clock gating programming into a display intel_display_clock_gating.c, to remove more dependencies from i915 to display registers. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-3-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm/i915: move SKL clock gating init to displayLuca Coelho
Move the SKL-specific display clock gating programming into a new file inside display. This removes dependency from intel_clock_gating.c to the display's intel_pch.h file, so we can remove the include statement. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260428095104.818360-2-luciano.coelho@intel.com Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2026-05-05drm: xlnx: zynqmp: Add support for XVUY2101010Tomi Valkeinen
Add support for XVUY2101010 format. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-11-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm: xlnx: zynqmp: Add support for T430Tomi Valkeinen
Add support for T430 format. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-10-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm: xlnx: zynqmp: Add support for Y8 and XYYY2101010Tomi Valkeinen
Add support for Y8 and XYYY2101010 formats. We also need to add new csc matrices for these y-only formats. Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-9-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm: xlnx: zynqmp: Add support for P030 & P230Tomi Valkeinen
Add support for P030 & P230 formats. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-8-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm: xlnx: zynqmp: Use drm helpers when calculating buffer sizesTomi Valkeinen
Use drm helpers, drm_format_info_plane_width(), drm_format_info_plane_height() and drm_format_info_min_pitch() to calculate sizes for the DMA. This cleans up the code, but also makes it possible to support more complex formats (like P030, P230). Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-7-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm/fourcc: Add DRM_FORMAT_XVUY2101010Tomi Valkeinen
Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit container. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Reviewed-by: Simon Ser <contact@emersion.fr> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-6-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2026-05-05drm/fourcc: Add DRM_FORMAT_T430Tomi Valkeinen
Add T430, a 3 plane 10 bits per component non-subsampled YCbCr format. A new initial letter was chosen for this one, as the format doesn't match the existing P, Q or S formats. T is the next one in the alphabet. It was definitely not chosen because of the initial letter in the author's name. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Simon Ser <contact@emersion.fr> Link: https://patch.msgid.link/20260423-xilinx-formats-v10-5-c690c2b8ea89@ideasonboard.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-17 09:55:53 +0000