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path: root/drivers/pinctrl
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2025-09-08pinctrl: mediatek: mt7988: use PINCTRL_PIN_FUNCTION()Bartosz Golaszewski
We have a dedicated initializer macro for defining pin functions for mediatek drivers so use it here. Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: airoha: replace struct function_desc with struct pinfunctionBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. This driver doesn't use the data pointer. We're also working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). Replace the struct function_desc objects in this driver with smaller struct pinfunction instances. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: ingenic: use struct pinfunction instead of struct function_descBartosz Golaszewski
struct function_desc is a wrapper around struct pinfunction with an additional void *data pointer. This driver doesn't use the data pointer. We're also working towards reducing the usage of struct function_desc in pinctrl drivers - they should only be created by pinmux core and accessed by drivers using pinmux_generic_get_function(). Replace the struct function_desc objects in this driver with smaller struct pinfunction instances. Acked-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: check the return value of pinmux_ops::get_function_name()Bartosz Golaszewski
While the API contract in docs doesn't specify it explicitly, the generic implementation of the get_function_name() callback from struct pinmux_ops - pinmux_generic_get_function_name() - can fail and return NULL. This is already checked in pinmux_check_ops() so add a similar check in pinmux_func_name_to_selector() instead of passing the returned pointer right down to strcmp() where the NULL can get dereferenced. This is normal operation when adding new pinfunctions. Cc: stable@vger.kernel.org Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: ma35: Use int type to store negative error codesQianfeng Rong
Change the 'ret' variable in ma35_pinctrl_parse_functions() from u32 to int, as it needs to store either negative error codes or zero returned by ma35_pinctrl_parse_groups(). No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: armada-37xx: Use int type to store negative error codesQianfeng Rong
In armada_37xx_gpio_direction_output(), the 'ret' variable might store the negative error codes returned by regmap_update_bits(), and in armada_37xx_edge_both_irq_swap_pol(), the 'ret' variable directly stores -1, so the type of the 'ret' variable needs to be changed to int in both cases. No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-09-08pinctrl: renesas: r8a779g0: Fix trivial typo in SoC type commentMarek Vasut
Fix SoC type comment in the PFC table file, replace R8A779A0 likely copy-paste error with R8A779G0. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250904222806.193260-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: Use int type to store negative error codesQianfeng Rong
Change the 'ret' variable in sh_pfc_pinconf_group_set() from unsigned int to int, as it needs to store either negative error codes or zero returned by sh_pfc_pinconf_set(). No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Fixes: d0593c363f04ccc4 ("pinctrl: sh-pfc: Propagate errors on group config") Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250831084958.431913-4-rongqianfeng@vivo.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control ↵Biju Das
registers Renesas RZ/G3E supports a power-saving mode where power to most of the SoC components is lost, including the PIN controller. Save and restore the Schmitt control register contents to ensure the functionality is preserved after a suspend/resume cycle. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250819084022.20512-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08pinctrl: renesas: rzg2l: Fix OEN resumeBiju Das
Writing to the PFC_OEN register is controlled by the write protect register (PWPR). Currently the OEN register write in resume() is done without enabling write access in PWPR leading to incorrect operation. Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [geert: Move spin_*lock*() calls inside if-statements] Link: https://lore.kernel.org/20250817143024.165471-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-08Merge tag 'v6.17-rc5' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next Linux 6.17-rc5
2025-09-03gpio: nomadik: don't print out global GPIO numbers in debugfs callbacksBartosz Golaszewski
In order to further limit the number of references to the GPIO base number stored in struct gpio_chip, replace the global GPIO numbers in the output of debugfs callbacks by hardware offsets. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250826-gpio-dbg-show-base-v1-2-7f27cd7f2256@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-09-02pinctrl: samsung: Drop unused S3C24xx driver dataKrzysztof Kozlowski
Drop unused declarations after S3C24xx SoC family removal in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"). Fixes: 1ea35b355722 ("ARM: s3c: remove s3c24xx specific hacks") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250830111657.126190-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-01pinctrl: samsung: Add ARTPEC-8 SoC specific configurationSeonGu Kang
Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30Merge tag 'renesas-pinctrl-for-v6.18-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.18 - Add support for Output Enable (OEN) on RZ/G3E, - Add support for the RZ/T2H and RZ/N2H SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-29drivers: firmware: xilinx: Switch to new family code in ↵Jay Buddhabhatti
zynqmp_pm_get_family_info() Currently, the family code and subfamily code are derived from the PMC_TAP_IDCODE register. Versal, Versal NET share the same family code. Also some platforms share the same subfamily code, making it difficult to distinguish between platforms. Update zynqmp_pm_get_family_info() to use IDs derived from the compatible string instead of silicon ID codes derived from PMC_TAP_IDCODE register. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20250701123851.1314531-4-jay.buddhabhatti@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-08-28pinctrl: meson-gxl: add missing i2c_d pinmuxDa Xue
Amlogic GXL has 4 I2C attached to gpio-periphs. I2C_D is on GPIOX_10/11. Add the relevant func 3 pinmux per the datasheet for S805X/S905X/S905D. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by: Da Xue <da@libre.computer> Link: https://lore.kernel.org/20250821233335.1707559-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-27pinctrl: Add pinctrl_pm_select_init_state helper functionChristian Bruel
If a platform requires an initial pinctrl state during probing, this helper function provides the client with access to the same initial state. eg: xxx_suspend_noirq ... pinctrl_pm_select_sleep_state xxx resume_noirq pinctrl_pm_select_init_state ... pinctrl_pm_select_default_state Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20250820075411.1178729-3-christian.bruel@foss.st.com
2025-08-22pinctrl: airoha: Fix return value in pinconf callbacksLorenzo Bianconi
Pinctrl stack requires ENOTSUPP error code if the parameter is not supported by the pinctrl driver. Fix the returned error code in pinconf callbacks if the operation is not supported. Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/20250822-airoha-pinconf-err-val-fix-v1-1-87b4f264ced2@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: amd: Don't access irq_data's hwirq member directlyMario Limonciello (AMD)
There is an irqd_to_hwirq() intended to get the hwirq number. Switch all use to it. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250821144942.2463014-1-superm1@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: STMFX: add missing HAS_IOMEM dependencyRandy Dunlap
When building on ARCH=um (which does not set HAS_IOMEM), kconfig reports an unmet dependency caused by PINCTRL_STMFX. It selects MFD_STMFX, which depends on HAS_IOMEM. To stop this warning, PINCTRL_STMFX should also depend on HAS_IOMEM. kconfig warning: WARNING: unmet direct dependencies detected for MFD_STMFX Depends on [n]: HAS_IOMEM [=n] && I2C [=y] && OF [=y] Selected by [y]: - PINCTRL_STMFX [=y] && PINCTRL [=y] && I2C [=y] && OF_GPIO [=y] Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/20250815022721.1650885-1-rdunlap@infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-22pinctrl: amd: Add PM debugging message for turning on/off wakesMario Limonciello (AMD)
The GPIOs for devices not in _AEI/_EVT such as touchpad or touchscreen won't have wakeup turned on until the suspend sequence starts. Due to code in amd_gpio_suspend_hibernate_common() masking the interrupt can make this difficult to follow what's going on. Add an explicit debugging message to tell when that was turned on/off. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://lore.kernel.org/20250814183430.3887973-2-superm1@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-21pinctrl: sunxi: use kcalloc() instead of kzalloc()Qianfeng Rong
Use devm_kcalloc() in init_pins_table() and prepare_function_table() to gain built-in overflow protection, making memory allocation safer when calculating allocation size compared to explicit multiplication. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/20250819143935.372084-5-rongqianfeng@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-21pinctrl: qcom: sc8180x: use kcalloc() instead of kzalloc()Qianfeng Rong
Use devm_kcalloc() in sc8180x_pinctrl_add_tile_resources() to gain built-in overflow protection, making memory allocation safer when calculating allocation size compared to explicit multiplication. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250819143935.372084-4-rongqianfeng@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-21pinctrl: pinctrl-zynqmp: use kcalloc() instead of kzalloc()Qianfeng Rong
Use devm_kcalloc() in versal_pinctrl_prepare_pin_desc() to gain built-in overflow protection, making memory allocation safer when calculating allocation size compared to explicit multiplication. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/20250819143935.372084-3-rongqianfeng@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-21pinctrl: microchip-sgpio: use kcalloc() instead of kzalloc()Qianfeng Rong
Use devm_kcalloc() in microchip_sgpio_register_bank() to gain built-in overflow protection, making memory allocation safer when calculating allocation size compared to explicit multiplication. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Link: https://lore.kernel.org/20250819143935.372084-2-rongqianfeng@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-20pinctrl: stm32: Constify static 'pinctrl_desc'Krzysztof Kozlowski
The local static 'struct pinctrl_desc' is not modified, so can be made const for code safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250818142402.132008-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-20pinctrl: renesas: rzt2h: Add support for RZ/N2HLad Prabhakar
The Renesas RZ/N2H (R9A09G087) SoC shares a similar pin controller architecture with the RZ/T2H (R9A09G077) SoC, differing primarily in the number of supported pins: 576 on RZ/N2H versus 729 on RZ/T2H. Add the necessary pin configuration data and compatible string to enable support for the RZ/N2H SoC in the RZ/T2H pinctrl driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250808133017.2053637-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-20pinctrl: renesas: Add support for RZ/T2HThierry Bultel
Add a pin control and GPIO driver for the Renesas RZ/T2H (R9A09G077) SoC. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250808133017.2053637-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-19pinctrl: sx150x: Make the driver tristateFange Zhang
Set PINCTRL_SX150X config option as a tristate and add MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate information. Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/20250818-modularize-sx150x-gpio-expander-v1-1-c2a027200fed@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: meson-g12a: add GPIOC_7 pcie_clkreqn pinmuxDa Xue
Amlogic G12 exposes PCIe clock request signal on GPIOC_7 pinmux func 1 Add the relevant pinmux and pin groups Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/20250814181236.1956731-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: remove unneeded 'fast_io' parameter in regmap_configWolfram Sang
When using MMIO with regmap, fast_io is implied. No need to set it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/20250813161517.4746-14-wsa+renesas@sang-engineering.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: equilibrium: Remove redundant semicolonsLiao Yuanhong
Remove unnecessary semicolons. Fixes: 1948d5c51dba4 ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") Signed-off-by: Liao Yuanhong <liaoyuanhong@vivo.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/20250812075444.8310-1-liaoyuanhong@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: tegra: Add Tegra186 pinmux driverAaron Kling
This is based on Nvidia's downstream 5.10 driver, rewritten to match the mainline Tegra194 pinmux driver. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/20250812-tegra186-pinctrl-v3-2-115714eeecb1@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: rp1: Add regmap ranges to RP1 gpio controllerAndrea della Porta
The current gpio driver for RP1 shows only the very first register from sysfs, e.g.: $ cat /sys/kernel/debug/regmap/1f000d0000.gpio-rp1-pinctrl/registers 0: 0abe0000 Add the correct ranges to the regmap configuration. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Link: https://lore.kernel.org/20250812092618.14270-1-andrea.porta@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: bcm: use PTR_ERR_OR_ZERO() to simplify codeXichao Zhao
Use the standard error pointer macro to shorten the code and simplify. Signed-off-by: Xichao Zhao <zhao.xichao@vivo.com> Link: https://lore.kernel.org/20250812081243.22659-1-zhao.xichao@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19Merge branch 'ib-gpio_generic_chip_init' into develLinus Walleij
2025-08-19pinctrl: wpcm450: use new generic GPIO chip APIBartosz Golaszewski
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-5-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: npcm7xx: use new generic GPIO chip APIBartosz Golaszewski
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-4-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: npcm8xx: use new generic GPIO chip APIBartosz Golaszewski
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-3-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: equilibrium: use new generic GPIO chip APIBartosz Golaszewski
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-2-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: stm32: use new generic GPIO chip APIBartosz Golaszewski
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-1-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-18pinctrl: Add pin controller driver for AAEON UP boardsThomas Richard
This enables the pin control support of the onboard FPGA on AAEON UP boards. This FPGA acts as a level shifter between the Intel SoC pins and the pin header, and also as a mux or switch. +---------+ +--------------+ +---+ | | | | | | PWM0 | \ | | H | |----------|------ \-----|-------------| E | | I2C0_SDA | | | A | Intel SoC |----------|------\ | | D | | GPIO0 | \------|-------------| E | |----------|------ | | R | | | FPGA | | | ----------+ +--------------+ +---+ For most of the pins, the FPGA opens/closes a switch to enable/disable the access to the SoC pin from a pin header. Each switch, has a direction flag that is set depending the status of the SoC pin. For some other pins, the FPGA acts as a mux, and routes one pin (or the other one) to the header. The driver also provides a GPIO chip. It requests SoC pins in GPIO mode, and drives them in tandem with FPGA pins (switch/mux direction). This commit adds support only for UP Squared board. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/20250811-aaeon-up-board-pinctrl-support-v9-10-29f0cbbdfb30@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-18pinctrl: single: fix bias pull up/down handling in pin_config_setChi Zhang
In the pin_config_set function, when handling PIN_CONFIG_BIAS_PULL_DOWN or PIN_CONFIG_BIAS_PULL_UP, the function calls pcs_pinconf_clear_bias() which writes the register. However, the subsequent operations continue using the stale 'data' value from before the register write, effectively causing the bias clear operation to be overwritten and not take effect. Fix this by reading the 'data' value from the register after calling pcs_pinconf_clear_bias(). This bug seems to have existed when this code was first merged in commit 9dddb4df90d1 ("pinctrl: single: support generic pinconf"). Signed-off-by: Chi Zhang <chizhang@asrmicro.com> Link: https://lore.kernel.org/20250807062038.13610-1-chizhang@asrmicro.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-18pinctrl: spacemit: remove extra line in debug outputHendrik Hamerlinck
The debug output for spacemit_pinconf_dbg_show() prints an extra newline at the end. This is redundant as pinconf_pins_show() in pinconf.c already adds a newline in its for loop. Remove the newline to avoid the extra line in the output. Example current output: $ cat /sys/kernel/debug/pinctrl/d401e000.pinctrl/pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (GPIO_00): , bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) pin 1 (GPIO_01): slew rate (0x0), bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) pin 2 (GPIO_02): slew rate (0x0), bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) ... Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20250805150701.129113-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-18pinctrl: meson: Fix typo in device table macroAlexey Gladkov
The typo when using the MODULE_DEVICE_TABLE macro was not noticeable because the macro was defined only if the module was built as a separate module. Cc: Xianwei Zhao <xianwei.zhao@amlogic.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-amlogic@lists.infradead.org Cc: linux-gpio@vger.kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202507220009.8HKbNP16-lkp@intel.com/ Signed-off-by: Alexey Gladkov <legion@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/e548b7761302defec15aa2098172eabb1ce1ad4a.1755170493.git.legion@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-11pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacksLad Prabhakar
Remove oen_read and oen_write callbacks from rzg2l_pinctrl_data as all SoCs now use the same rzg2l_read_oen() and rzg2l_write_oen() functions directly. Change rzg2l_read_oen() return type to int for proper error reporting and update callers to handle errors consistently. This simplifies the code by removing redundant callbacks and ensures uniform OEN handling across all supported SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806195555.1372317-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoCLad Prabhakar
Add support for configuring the PFC_OEN register on the RZ/G3E SoC to enable output-enable control for specific pins. On this SoC, certain pins such as TXC_TXCLK need to support switching between input and output modes depending on the PHY interface mode (e.g., MII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the PFC_OEN register. This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1, PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these pin names to their respective OEN bit positions, and the corresponding callbacks are wired into the RZ/G3E SoC configuration using the generic rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO configuration for the PB, PE, and PL ports is updated to use the variable port pack macro, enabling per-pin configuration necessary for OEN handling. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806195555.1372317-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}Lad Prabhakar
Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded PFC_OEN define and obsolete per-SoC OEN helpers. Also drop redundant checks for the OEN offset in the suspend/resume paths, as all supported SoCs now provide a valid offset through the `regs.oen` field. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806195555.1372317-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3ELad Prabhakar
The RZ/G3E pin controller does not advertise PIN_CFG_OEN capability, so there is no valid mapping for output-enable bits on this SoC. Remove the oen_read and oen_write callbacks from the RZ/G3E driver data to defer OEN support until PIN_CFG_OEN support is added. This is a preparatory change for future unification of OEN handling across the driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806195555.1372317-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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