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path: root/drivers/pinctrl
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2025-04-17pinctrl: qcom: msm: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250410-gpiochip-set-rv-pinctrl-qcom-v1-2-6a6891338aae@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-17pinctrl: qcom: lpass-lpi: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250410-gpiochip-set-rv-pinctrl-qcom-v1-1-6a6891338aae@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-17pinctrl: qcom: pinctrl-qcm2290: Add egpio supportWojciech Slenska
qcm2290 supports the egpio feature on GPIOs ranging from 98 to 126. This change is necessary to allow these GPIOs to be driven by TLMM. Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250409080030.62254-1-wojciech.slenska@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-17pinctrl: cy8c95x0: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-10-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-17pinctrl: ocelot: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-9-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-17pinctrl: sx150x: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-8-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: amlogic-a4: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-6-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-5-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: abx500: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-4-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: abx500: enable building modules with COMPILE_TEST=yBartosz Golaszewski
Increase the build coverage by enabling the abx500 modules with COMPILE_TEST=y. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-3-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: rk805: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-2-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: at91-pio4: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-1-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: uniphier: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250404115719.309999-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250404115719.309999-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: airoha: fix wrong PHY LED mapping and PHY2 LED definesChristian Marangi
The current PHY2 LED define are wrong and actually set BITs outside the related mask. Fix it and set the correct value. While at it, also use FIELD_PREP_CONST macro to make it simple to understand what values are actually applied for the mask. Also fix wrong PHY LED mapping. The SoC Switch supports up to 4 port but the register define mapping for 5 PHY port, starting from 0. The mapping was wrongly defined starting from PHY1. Reorder the function group to start from PHY0. PHY4 is actually never supported as we don't have a GPIO pin to assign. Cc: stable@vger.kernel.org Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC") Reviewed-by: Benjamin Larsson <benjamin.larsson@genexis.eu> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/20250401135026.18018-1-ansuelsmth@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: define the pull up/down resistor value as 60 kOhmMartin Blumenstingl
The public datasheets of the following Amlogic SoCs describe a typical resistor value for the built-in pull up/down resistor: - Meson8/8b/8m2: not documented - GXBB (S905): 60 kOhm - GXL (S905X): 60 kOhm - GXM (S912): 60 kOhm - G12B (S922X): 60 kOhm - SM1 (S905D3): 60 kOhm The public G12B and SM1 datasheets additionally state min and max values: - min value: 50 kOhm for both, pull-up and pull-down - max value for the pull-up: 70 kOhm - max value for the pull-down: 130 kOhm Use 60 kOhm in the pinctrl-meson driver as well so it's shown in the debugfs output. It may not be accurate for Meson8/8b/8m2 but in reality 60 kOhm is closer to the actual value than 1 Ohm. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250329190132.855196-1-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: apple: Make regmap_config static const and fix indentationJohn Madieu
Mark the regmap_config as static const since it is only used in this file and never modified, allowing the compiler to optimize it and enforce const-correctness. Also fix minor indentation inconsistencies in function parameter alignment to conform with kernel coding style. Signed-off-by: John Madieu <john.madieu@labcsmart.com> Link: https://lore.kernel.org/20250329181506.890043-1-john.madieu@labcsmart.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: mediatek: Fix the invalid conditionsHao Chang
The variable count_reg_names is defined as an int type and cannot be directly compared to an unsigned int. To resolve this issue, first verify the correctness of count_reg_names. Link: https://lore.kernel.org/all/5ae93d42e4c4e70fb33bf35dcc37caebf324c8d3.camel@mediatek.com/T/ Signed-off-by: Hao Chang <ot_chhao.chang@mediatek.com> Signed-off-by: Qingliang Li <qingliang.li@mediatek.com> Link: https://lore.kernel.org/20250329024533.5279-1-ot_chhao.chang@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: imx: Return NULL if no group is matched and foundHui Wang
Currently if no group is matched and found, this function will return the last grp to the caller, this is not expected, it is supposed to return NULL in this case. Fixes: e566fc11ea76 ("pinctrl: imx: use generic pinctrl helpers for managing groups") Signed-off-by: Hui Wang <hui.wang@canonical.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/20250327031600.99723-1-hui.wang@canonical.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: qcom: tlmm-test: Fix potential null dereference in tlmm kunit testCharles Han
kunit_kzalloc() may return a NULL pointer, dereferencing it without NULL check may lead to NULL dereference. Add a NULL check for grp. Fixes: c7984dc0a2b9 ("pinctrl: qcom: Add test case for TLMM interrupt handling") Signed-off-by: Charles Han <hanchunchao@inspur.com> Link: https://lore.kernel.org/20250325094932.4733-1-hanchunchao@inspur.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: mcp23s08: Reset all pins to input at probeMike Looijmans
At startup, the driver just assumes that all registers have their default values. But after a soft reset, the chip will just be in the state it was, and some pins may have been configured as outputs. Any modification of the output register will cause these pins to be driven low, which leads to unexpected/unwanted effects. To prevent this from happening, set the chip's IO configuration register to a known safe mode (all inputs) before toggling any other bits. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lore.kernel.org/20250314151803.28903-1-mike.looijmans@topic.nl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-11pinctrl: at91: Add error handling for pinctrl_utils_add_map_mux()Wentao Liang
In atmel_pctl_dt_subnode_to_map(), the return value of pinctrl_utils_add_map_mux() needs to be checked, for the function will fail to associate group when the group map is full. Add error handling for pinctrl_utils_add_map_mux() to return immediately and propagate the error code to caller function when the function fails. Signed-off-by: Wentao Liang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/20250318030717.781-1-vulab@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-09pinctrl: amd: Add an LPS0 check() callbackMario Limonciello
During suspend the pinctrl_amd driver disables the interrupts for any GPIOs that are not marked as wake sources. This however does not prevent them from changing the wake status bit during suspend, it just stops the system from waking. If the system wakes from hardware sleep for another reason (such as plugging in the AC adapter) this wake bits might be active. This could potentially cause problems with going back to hardware sleep. Add an extra debugging message when PM debugging is enabled to help identify if this is happening. Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3929 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20250407183656.1503446-2-superm1@kernel.org Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-04-08pinctrl: samsung: Add filter selection support for alive bank on gs101Peter Griffin
Newer Exynos based SoCs have a filter selection bitfield in the filter configuration registers on alive bank pins. This allows the selection of a digital or analog delay filter for each pin. Add support for selecting and enabling the filter. On suspend we set the analog filter to all pins in the bank (as the digital filter relies on a clock). On resume the digital filter is reapplied to all pins in the bank. The digital filter is working via a clock and has an adjustable filter delay flt_width bitfield, whereas the analog filter uses a fixed delay. The filter determines to what extent signal fluctuations received through the pad are considered glitches. The code path can be exercised using echo mem > /sys/power/state And then wake the device using a eint gpio Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-4-78ce0d4eb30c@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-08pinctrl: samsung: add gs101 specific eint suspend/resume callbacksPeter Griffin
gs101 differs to other SoCs in that fltcon1 register doesn't always exist. Additionally the offset of fltcon0 is not fixed and needs to use the newly added eint_fltcon_offset variable. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") Cc: stable@vger.kernel.org # depends on the previous three patches Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-3-78ce0d4eb30c@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-08pinctrl: samsung: add dedicated SoC eint suspend/resume callbacksPeter Griffin
Refactor the existing platform specific suspend/resume callback so that each SoC variant has it's own callback containing the SoC specific logic. This allows exynosautov920 to have a dedicated function for using eint_con_offset and eint_mask_offset. Also it is easily extendable for gs101 which will need dedicated logic for handling the varying register offset of fltcon0 via eint_fltcon_offset. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-2-78ce0d4eb30c@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-08pinctrl: samsung: refactor drvdata suspend & resume callbacksPeter Griffin
This enables the clk_enable() and clk_disable() logic to be removed from each callback, but otherwise should have no functional impact. It is a prepatory patch so that the callbacks can become SoC specific. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-1-78ce0d4eb30c@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-29Merge tag 'pinctrl-v6.15-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - None really. New drivers: - AMD ISP411 "AMD ISP" driver - Exynos 2200 and 7870 SoC subdrivers - Sophgo RISC-V SG2042 and SG2044 subdrivers - Amlogic A4 subdriver - Rockchip RK3528 subdriver - Broadcom BCM21664 subdriver - Allwinner A523/T527 subdriver - Ingenic X1600 subdriver - Microchip SAMA7D65 subdriver, essentially a re-branded Atmel AT91 PIO4 driver, but nowadays a Microschip SoC line Improvements: - Bring in the devm_kmemdup_array() helper and use it throughout, also bring in changes to other subsystems for this to establish this helper - Support EGPIO on the Qualcomm SA8775P SoC - Extend EINT support in the Mediatek driver" * tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (101 commits) pinctrl: mediatek: Add EINT support for multiple addresses pinctrl: amlogic-a4: Drop surplus semicolon pinctrl: nuvoton: Reduce use of OF-specific APIs pinctrl: nuvoton: Convert to use struct group_desc pinctrl: nuvoton: Make use of struct pinfunction and PINCTRL_PINFUNCTION() pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP() pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignment pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group() pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISP pinctrl: qcom: sa8775p: Enable egpio function dt-bindings: pinctrl: qcom: Add egpio function for sa8775p pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqs pinctrl: qcom: Clear latched interrupt status when changing IRQ type dt-bindings: pinctrl: airoha: Add missing gpio-ranges property pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all() pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe() dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl pinctrl: tegra: Set SFIO mode to Mux Register pinctrl-tegra: Restore SFSEL bit when freeing pins pinctrl: tegra: Add descriptions for SoC data fields ...
2025-03-24pinctrl: mediatek: Add EINT support for multiple addressesHao Chang
For flexible routing, eint will be divided into 5 bases, and it will obtain the operation address through the pins array. Signed-off-by: Hao Chang <ot_chhao.chang@mediatek.com> Signed-off-by: Qingliang Li <qingliang.li@mediatek.com> Link: https://lore.kernel.org/20250322035307.4811-2-ot_chhao.chang@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-22pinctrl: amlogic-a4: Drop surplus semicolonLinus Walleij
The kernel bots complain about untidy code found using coccinelle, fix it up. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202503212354.Hx2qaDRe-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: nuvoton: Reduce use of OF-specific APIsAndy Shevchenko
Some drivers are using device property APIs along with OF-specific ones. At the same time few of the latter can be converted to device property calls. Reduce use of OF-specific APIs in order to bring a bit more consistency into the drivers. Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: nuvoton: Convert to use struct group_descAndy Shevchenko
The pin control core header provides struct group_desc. Utilize it instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: nuvoton: Make use of struct pinfunction and PINCTRL_PINFUNCTION()Andy Shevchenko
Since pin control provides a generic data type and a macro for the pin function definition, use them in the driver. Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP()Andy Shevchenko
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro. Utilize them instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignmentAndy Shevchenko
Sparse is not happy about implementation of the NPCM8XX_PINCFG() pinctrl-npcm8xx.c:1314:9: warning: obsolete array initializer, use C99 syntax pinctrl-npcm8xx.c:1315:9: warning: obsolete array initializer, use C99 syntax ... pinctrl-npcm8xx.c:1412:9: warning: obsolete array initializer, use C99 syntax pinctrl-npcm8xx.c:1413:9: warning: too many warnings which uses index-based assignment in a wrong way, i.e. it missed the equal sign and hence the index is simply ignored, while the entries are indexed naturally. This is not a problem as the pin numbering repeats the natural order, but it might be in case of shuffling the entries. Fix this by adding missed equal sign and reformat a bit for better readability. Fixes: acf4884a5717 ("pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250318105932.2090926-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-20pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()Dan Carpenter
This should be >= pmx->soc->ngroups instead of > to avoid an out of bounds access. The pmx->soc->groups[] array is allocated in tegra_pinctrl_probe(). Fixes: c12bfa0fee65 ("pinctrl-tegra: Restore SFSEL bit when freeing pins") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Kunwu Chan <kunwu.chan@linux.dev> Link: https://lore.kernel.org/82b40d9d-b437-42a9-9eb3-2328aa6877ac@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-18pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISPGeert Uytterhoeven
The AMD Image Signal Processor GPIO pin control functionality is only present on AMD platforms with ISP support, and its platform device is instantiated by the AMD ISP driver. Hence add a dependency on DRM_AMD_ISP, to prevent asking the user about this driver when configuring a kernel that does not support the AMD ISP. Fixes: e97435ab09f3ad7b ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/3685561e8e3cd1d94bce220eeb6001d659da615c.1742306024.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-18pinctrl: spacemit: PINCTRL_SPACEMIT_K1 should not default to y unconditionallyGeert Uytterhoeven
Merely enabling compile-testing should not enable additional functionality. Fixes: 7ff4faba63571c51 ("pinctrl: spacemit: enable config option") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Tested-by: Alex Elder <elder@riscstar.com> Reviewed-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/6881b8d1ad74ac780af8a974e604b5ef3f5d4aad.1742198691.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-18Merge tag 'samsung-pinctrl-6.15' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.15 1. Add pin controller drivers for newly usptreamed Samsung Exynos2200 and Exynos7870. 2. Correct filter configuration offset of some of Google GS101 SoC pin banks, which later is supposed to be used during system suspend/resume. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: sa8775p: Enable egpio functionWasim Nazir
Egpio feature allows IsLand Domain IOs to be reused as TLMM GPIOs. sa8775p supports egpio feature for GPIOs ranging from 126 to 148. Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Link: https://lore.kernel.org/20250312072509.3247885-3-quic_wasimn@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqsBjorn Andersson
In commit 'cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling")' Doug establishes an expectation that edge interrupts occurring while an interrupt is disabled should be delivered once the interrupt is enabled again. Implement a test to validate that this is the case. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/20250313-tlmm-test-disabled-irq-delivered-v1-1-f0be903732ac@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: Clear latched interrupt status when changing IRQ typeStephan Gerhold
When submitting the TLMM test driver, Bjorn reported that some of the test cases are failing for GPIOs that not are backed by PDC (i.e. "non-wakeup" GPIOs that are handled directly in pinctrl-msm). Basically, lingering latched interrupt state is still being delivered at IRQ request time, e.g.: ok 1 tlmm_test_silent_rising tlmm_test_silent_falling: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 2 tlmm_test_silent_falling tlmm_test_silent_low: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 3 tlmm_test_silent_low ok 4 tlmm_test_silent_high Whether to report interrupts that came in while the IRQ was unclaimed doesn't seem to be well-defined in the Linux IRQ API. However, looking closer at these specific cases, we're actually reporting events that do not match the interrupt type requested by the driver: 1. After "ok 1 tlmm_test_silent_rising", the GPIO is in low state and configured for IRQF_TRIGGER_RISING. 2. (a) In preparation for "tlmm_test_silent_falling", the GPIO is switched to high state. The rising interrupt gets latched. (b) The GPIO is re-configured for IRQF_TRIGGER_FALLING, but the latched interrupt isn't cleared. (c) The IRQ handler is called for the latched interrupt, but there wasn't any falling edge. 3. (a) For "tlmm_test_silent_low", the GPIO remains in high state. (b) The GPIO is re-configured for IRQF_TRIGGER_LOW. This seems to result in a phantom interrupt that gets latched. (c) The IRQ handler is called for the latched interrupt, but the GPIO isn't in low state. 4. (a) For "tlmm_test_silent_high", the GPIO is switched to low state. (b) This doesn't result in a latched interrupt, because RAW_STATUS_EN was cleared when masking the level-triggered interrupt. Fix this by clearing the interrupt state whenever making any changes to the interrupt configuration. This includes previously disabled interrupts, but also any changes to interrupt polarity or detection type. With this change, all 16 test cases are now passing for the non-wakeup GPIOs in the TLMM. Cc: stable@vger.kernel.org Fixes: cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling") Reported-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Closes: https://lore.kernel.org/r/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com/ Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20250312-pinctrl-msm-type-latch-v1-1-ce87c561d3d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all()Dan Carpenter
The next line checks if this regmap_write() failed, but it doesn't work because the assignment was accidentally left out. Add the assignment. Fixes: 60d69769c851 ("pinctrl: bcm281xx: Add support for BCM21664 pinmux") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/dfc15d59-7fa9-4f96-aacb-37c3df6d420d@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe()Dan Carpenter
The platform_get_resource() returns NULL on error. It doesn't return error pointers. Fix the error checking to match. Fixes: e97435ab09f3 ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Link: https://lore.kernel.org/617f4c77-7837-4e24-9f4d-620ecfedf924@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: tegra: Set SFIO mode to Mux RegisterPrathamesh Shete
Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl-tegra: Restore SFSEL bit when freeing pinsPrathamesh Shete
Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: tegra: Add descriptions for SoC data fieldsPrathamesh Shete
Add detailed descriptions for the remaining fields in the tegra_pinctrl_soc_data structure. This improves code documentation and clarifies the purpose of each field, particularly for the pin-specific configuration options. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: spacemit: destroy mutex at driver detachBartosz Golaszewski
The mutex initialized in probe() is never cleaned up. Use devm_mutex_init() to destroy it automatically. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20250305102710.52762-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: ingenic: jz4730: add pinmux for I2S interfaceH. Nikolaus Schaller
I2S is used for the sound codec of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/7e79b16be569fb0f501032b2b6ec726e4a09411f.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: ingenic: jz4730: add pinmux for MIIH. Nikolaus Schaller
The MII interface is used for the Ethernet connection of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/972b31e1fce03808745e53df17315b29e2bcf696.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 23:23:25 +0000