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2026-05-29EDAC/{skx_common,skx}: Fix UBSAN shift-out-of-bounds in skx_get_dimm_infozhoumin
When the skx_get_dimm_attr() helper returns -EINVAL, skx_get_dimm_info() does not validate these return values before using them in a shift operation: size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); If all three values are -22, the shift exponent becomes -66, triggering a UBSAN shift-out-of-bounds error: UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c shift exponent -66 is negative Fixes: 88a242c98740 ("EDAC, skx_common: Separate common code out from skx_edac") Signed-off-by: zhoumin <teczm@foxmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/tencent_2A0CC835A18366643CBD2865B169948AB409@qq.com
2026-05-29EDAC/igen6: Add one Intel Panther Lake-H SoC supportQiuxu Zhuo
Add one Intel Panther Lake-H SoC compute die ID for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-4-qiuxu.zhuo@intel.com
2026-05-29EDAC/igen6: Fix memory topology parsing for Panther Lake-H SoCsQiuxu Zhuo
Panther Lake-H SoC memory controller registers for memory topology have been updated, but the current igen6_edac driver still uses old generation ones to incorrectly parse memory topology. Fix the issue by adding memory topology parsing function pointers to the 'struct res_config' and creating a new configuration structure for Panther Lake-H SoCs to enable igen6_edac to parse memory correctly. Fixes: 0be9f1af3902 ("EDAC/igen6: Add Intel Panther Lake-H SoCs support") Fixes: 4c36e6106997 ("EDAC/igen6: Add more Intel Panther Lake-H SoCs support") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-3-qiuxu.zhuo@intel.com
2026-05-29EDAC/igen6: Fix call trace due to missing release()Qiuxu Zhuo
When unloading the igen6_edac driver, there is a call trace: Device '(null)' does not have a release() function, it is broken and must be fixed. See Documentation/core-api/kobject.rst. WARNING: drivers/base/core.c:2567 at device_release+0x84/0x90, CPU#5: rmmod/127209 ... RIP: 0010:device_release+0x84/0x90 Call Trace: <TASK> kobject_put+0x8c/0x220 put_device+0x17/0x30 igen6_unregister_mcis+0xa2/0xe0 [igen6_edac] igen6_remove+0x82/0xb0 [igen6_edac] ... Fix the call trace by providing empty release() functions for the memory controller devices. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-2-qiuxu.zhuo@intel.com
2026-05-29EDAC/sb_edac: fix grammar in sb_decode_ddr3 warningThorsten Blum
Fix the warning in sb_decode_ddr3() by adding the missing verb "is" and using "supported" instead of "support" to match the LockStep warning in sb_decode_ddr4(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260508143844.2996-3-thorsten.blum@linux.dev
2026-05-29EDAC/i5400: disable error reporting at teardown and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver teardown, error reporting is left enabled in the mask register even after exit. Replace i5400_enable_error_reporting() with i5400_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i5400_put_devices() for cleanup. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-4-tushar.tibude1000@gmail.com
2026-05-29EDAC/i5100: disable error reporting at teardown and create helperTushar Tibude
Error reporting is enabled during init but not reverted when init fails. It is also not disabled at normal driver teardown. Create i5100_set_error_reporting() to enable/disable reporting. Move enable reporting write to after initialization success. Disable reporting at driver teardown. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-3-tushar.tibude1000@gmail.com
2026-05-29EDAC/i5000: disable error reporting at teardown and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver teardown, error reporting is left enabled in the mask register even after exit. Replace i5000_enable_error_reporting() with i5000_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i5000_put_devices() for cleanup. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-2-tushar.tibude1000@gmail.com
2026-05-29EDAC/i7300: disable error reporting if init fails and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver exit, error reporting is left enabled in the mask register even after exit. Replace i7300_enable_error_reporting() with i7300_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i7300_put_devices() for cleanup. Add enabled reporting flag to i7300_pvt. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260429094806.25097-1-tushar.tibude1000@gmail.com
2026-05-29remoteproc: xlnx: Enable auto boot featureTanmay Shah
The remoteproc framework has capability to start (or attach to) the remote processor automatically if auto boot flag is set by the driver during probe. If the 'firmware-name' property is available for the remoteproc node, then that firmware will be loaded and started during auto boot. If the remote core is started by the bootloader then during auto-boot remoteproc framework will try to attach to the remote processor. The current architecture allocates and adds the remoteproc instance before all the hardware such as sram, mbox, TCM is initialized. This design has to be changed for auto boot to work. So, rename zynqmp_r5_rproc_add() function to zynqmp_r5_rproc_alloc() and move adding the remoteproc instance at the end of cluster initialization. This makes sure that all the required hardware is initialized before starting the remote processor. Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Link: https://lore.kernel.org/r/20260527051611.194844-3-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2026-05-29mmc: Merge branch fixes into nextUlf Hansson
Merge the mmc fixes for v7.1-rc[n] into the next branch, to allow them to get tested together with the mmc changes that are targeted for the next release. Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29drm/msm/adreno: add Adreno 810 GPU supportAlexander Koskovich
Add catalog entry and register configuration for the Adreno 810 found in Qualcomm SM7635 (Milos) based devices. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Patchwork: https://patchwork.freedesktop.org/patch/728812/ Message-ID: <20260528-adreno-810-v7-6-7fe7fdd97fc2@pm.me> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound featureAlexander Koskovich
A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Patchwork: https://patchwork.freedesktop.org/patch/728810/ Message-ID: <20260528-adreno-810-v7-5-7fe7fdd97fc2@pm.me> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCCAlexander Koskovich
Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Patchwork: https://patchwork.freedesktop.org/patch/728808/ Message-ID: <20260528-adreno-810-v7-4-7fe7fdd97fc2@pm.me> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/adreno: rename llc_mmio to cx_misc_mmioAlexander Koskovich
This region is used for more than just LLCC, it also provides access to software fuse values (raytracing, etc). Rename relevant symbols from _llc to _cx_misc for use in a follow up change that decouples this from LLCC. Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Patchwork: https://patchwork.freedesktop.org/patch/728806/ Message-ID: <20260528-adreno-810-v7-3-7fe7fdd97fc2@pm.me> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx: Allow IFPC with perfcntr streamRob Clark
Now that the dynamic pwrup reglist has SEL reg values to restore appended, so that SEL regs are restored on IFPC exit, we can stop completely disabling IFPC while global counter sampling is active. To accomplish this, we re-use sysprof_setup() with a force_on param to inhibit IFPC specifically while the counter regs are being read, while leaving IFPC enabled the rest of the time. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728219/ Message-ID: <20260526145137.160554-17-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx: Append SEL regs to dyn pwrup reglistRob Clark
This is needed so that SEL reg values are restored on exit from IFPC. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728218/ Message-ID: <20260526145137.160554-16-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx: Increase pwrup_reglist sizeRob Clark
To make room for appending SEL reg programming. Without increasing the size, we would overflow the pwrup_reglist at ~190 counters on gen8. Or possibly fewer, considering that some gen8 counter groups also have separate slice vs unslice SELectors. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728228/ Message-ID: <20260526145137.160554-15-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Add PERFCNTR_CONFIG ioctlRob Clark
Add new UABI and implementation of PERFCNTR_CONFIG ioctl. A bit more work is required to configure the pwrup_reglist for the GMU to restore SELect regs on exit of IFPC, before we can stop disabling IFPC while global counter collection. This will follow in a later commit, but will be transparent to userspace. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728217/ Message-ID: <20260526145137.160554-14-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a8xx: Add perfcntr flush sequenceRob Clark
With the slice architecture, we need to flush the slice and unslice counters to perf RAM before reading counters. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728216/ Message-ID: <20260526145137.160554-13-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx+: Add support to configure perfcntrsRob Clark
Add support to configure counter SELect regs. In some cases the reg writes need to happen while the GPU is idle. And for a7xx+, in some cases SEL regs need to be configured from BV or BR aperture. The easiest way to deal with this is to configure from the RB. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728215/ Message-ID: <20260526145137.160554-12-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Add basic perfcntr infrastructureRob Clark
Add the basic infrastructure for tracking assigned perfcntrs. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728212/ Message-ID: <20260526145137.160554-11-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Add per-context perfcntr stateRob Clark
The upcoming PERFCNTR_CONFIG ioctl will allow for both global counter collection, and per-context counter reservation for local (ie. within a single GEM_SUBMIT ioctl) counter collection. Any number of contexts can reserve the same counters, but we will need to ensure that counters reserved for local counter collection do not conflict with counters used for global counter collection. So add tracking for per-context local counter reservations. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728211/ Message-ID: <20260526145137.160554-10-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx: Add yield & flush helperRob Clark
It's a common pattern, needing to insert a yield packet before flushing the rb. And we'll need this once again for configuring perfcntr SEL regs. So add a helper. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728208/ Message-ID: <20260526145137.160554-9-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Add sysprof accessorsRob Clark
Currently the sysprof param serves two functions, (a) disabling perfcntr clearing on context switch/preemption, and (b) disabling IFPC. In the future, with kernel side global perfcntr collection/stream, the decision about disabling IFPC will change. To prepare for this, split out two helpers/accessors for the two different cases. For now, they are the same thing, but this will change. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728214/ Message-ID: <20260526145137.160554-8-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Add a6xx+ perfcntr tablesRob Clark
Wire up the generated perfcntr tables for a6xx+. The PERFCNTR_CONFIG ioctl will use this information to assign counters. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728213/ Message-ID: <20260526145137.160554-7-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/registers: Add perfcntr jsonRob Clark
Pull in perfcntr json and wire up generation of perfcntr tables. Sync from mesa commit a573e25b6dcd ("freedreno/registers: Gen8 perfcntr fixes") Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728204/ Message-ID: <20260526145137.160554-6-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/registers: Sync gen_header.py from mesaRob Clark
Update gen_header.py to bring in support for generating perfcntr tables. Sync from mesa commit 96c5179c02d1 ("freedreno/registers: Skip deprecated warns for kernel") Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728203/ Message-ID: <20260526145137.160554-5-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/adreno: Sync registers from mesaRob Clark
Most of the churn is just reworking the usage attribute on the mesa side. Sync from mesa commit ff41a00fab89 ("freedreno/registers: Correct register name") Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728202/ Message-ID: <20260526145137.160554-4-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Allow CAP_PERFMON for setting SYSPROFRob Clark
Use perfmon_capable() which checks both CAP_SYS_ADMIN and CAP_PERFMON. This matches what i915 and xe do, and seems more appropriate. Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728198/ Message-ID: <20260526145137.160554-3-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm: Remove obsolete perf infrastructureRob Clark
Outside of a3xx, this was never really used. And it low-key gets in the way of the new perfcntr support (or at least it is confusing to have two things called "perf"). So lets remove it. This drops the "perf" debugfs file. But these days, nvtop is a better option. (Plus perfetto for newer gens.) Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/728200/ Message-ID: <20260526145137.160554-2-robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a8xx: Fix RSCC offsetAkhil P Oommen
In A8xx, the RSCC block is part of GPU's register space. Update the virtual base address of rscc to point to the correct address. Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/727117/ Message-ID: <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a6xx: Limit GXPD votes to recovery in A8xAkhil P Oommen
In A8x GPUs, the GX GDSC is moved to a separate block called GXCLKCTL which is under the GX power domain. Due to the way the support for this block is implemented in its driver, pm_runtime votes result in a vote on GX/GMxC/MxC rails from the APPS RSC. This is against the Adreno architecture which require GMU to be the sole voter of these collapsible rails on behalf of GPU, except during the GPU/GMU recovery. To align with this architectural requirement and to realize the power benefits of the IFPC feature, remove the GXPD votes during gmu resume and suspend. And during the recovery sequence, enable/disable the GXPD along with the 'synced_poweroff' genpd hint to force collapse this GDSC. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/720979/ Message-ID: <20260427-gfx-clk-fixes-v2-6-797e54b3d464@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29drm/msm/a8xx: Make a8xx_recover IFPC safeAkhil P Oommen
Similar to a6xx_recover(), check the GX power domain status before accessing mmio in GX domain a8xx_recover(). Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/720977/ Message-ID: <20260427-gfx-clk-fixes-v2-5-797e54b3d464@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-05-29firmware: samsung: acpm: remove compile-testing stubsArnd Bergmann
Sashiko reported an inconsistent use of NULL vs ERR_PTR() returns in the stub helpers in xynos-acpm-protocol.h. Since this only happens on dead code for COMPILE_TEST=y, this is not really a bug though. Having stub functions that return NULL is a common way to define optional interfaces, where callers still work when the feature is disabled, though this clearly does not work for acpm because some callers have a NULL pointer dereference when compile testing. Since CONFIG_EXYNOS_ACPM_PROTOCOL already supports compile-testing itself, and all (both) drivers using it clearly require the support, so this just simplifies the option space without losing any build coverage. Remove the stub functions entirely and adjust the one Kconfig dependency to require EXYNOS_ACPM_PROTOCOL unconditionally. Fixes: 6837c006d4e7 ("firmware: exynos-acpm: add empty method to allow compile test") Closes: https://sashiko.dev/#/patchset/20260420-acpm-tmu-v3-0-3dc8e93f0b26%40linaro.org Link: https://lore.kernel.org/all/a7994860-24a3-4f87-84bf-109ed653dda4@linaro.org/ Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260529134454.2147446-1-arnd@kernel.org [krzk: Rebase on difference in devm_acpm_get_by_node()] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Add devm_acpm_get_by_phandle helperTudor Ambarus
Introduce devm_acpm_get_by_phandle() to standardize how consumer drivers acquire a handle to the ACPM IPC interface. Enforce the use of the "samsung,acpm-ipc" property name across the SoC and simplify the boilerplate code in client drivers. The first consumer of this helper is the Exynos ACPM Thermal Management Unit (TMU) driver. The TMU utilizes a hybrid management approach: direct register access from the Application Processor (AP) is restricted to the interrupt pending (INTPEND) registers for event identification. High-level functional tasks, such as sensor initialization, threshold programming, and temperature reads, are delegated to the ACPM firmware via this IPC interface. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-6-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Add TMU protocol supportTudor Ambarus
The Thermal Management Unit (TMU) on the Google GS101 SoC is managed through a hybrid model shared between the kernel and the Alive Clock and Power Manager (ACPM) firmware. Add the protocol helpers required to communicate with the ACPM for thermal operations, including initialization, threshold configuration, temperature reading, and system suspend/resume handshakes. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-5-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Make acpm_ops const and access via pointerTudor Ambarus
Replace the embedded `struct acpm_ops` inside `struct acpm_handle` with a pointer to a `const struct acpm_ops`. Previously, the operations structure was embedded directly within the handle and populated dynamically at runtime via `acpm_setup_ops()`. This resulted in mutable function pointers and unnecessary per-instance memory overhead. By defining `exynos_acpm_driver_ops` statically as a `const` structure, the function pointers are now safely housed in the read-only `.rodata` section. This improves security by preventing function pointer overwrites, saves memory, and slightly reduces initialization overhead in `acpm_probe()`. Consequently, update all consumer drivers (clk, mfd) to access the operations via the new pointer indirection (`->ops->`). Finally, fix the previously empty kernel-doc description for the ops member to reflect its new pointer nature. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-4-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops membersTudor Ambarus
Rename the `dvfs_ops` and `pmic_ops` members of `struct acpm_ops` to `dvfs` and `pmic` respectively. Since these members are housed within the `acpm_ops` structure and utilize the `acpm_*_ops` types, the `_ops` suffix on the variable names creates unnecessary redundancy (e.g., `handle.ops.dvfs_ops`). This cleanup removes the stuttering, leading to cleaner consumer code. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/linux-samsung-soc/CADrjBPqzKpcd9vuCmNUptCUPyPpPbHcc19-7kN-1c0RpW1e5DQ@mail.gmail.com/T/#mcce154a7e0c6cd1ca6cd5a1e37541ed7a85a84d4 [1] Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-3-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptrTudor Ambarus
Rename the `n_cmd` member of `struct acpm_rx_data` to `cmdcnt` to maintain consistent nomenclature across the driver (aligning with `txcnt`, `rxcnt`, and transfer helpers). With the member renamed, annotate the dynamically allocated `cmd` pointer with the `__counted_by_ptr(cmdcnt)` macro to improve runtime bounds checking. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-2-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29firmware: samsung: acpm: Consolidate transfer initialization helperTudor Ambarus
Both the DVFS and PMIC ACPM sub-drivers implement similar local helper functions (acpm_dvfs_set_xfer and acpm_pmic_set_xfer) to initialize the acpm_xfer structure before sending an IPC message. Move this logic into a single centralized helper, acpm_set_xfer(), in the core ACPM driver to reduce boilerplate, eliminate code duplication, and prepare for the upcoming ACPM TMU helper sub-driver which will also utilize this method. Note that there is no change in underlying functionality. While the old acpm_pmic_set_xfer() unconditionally assigned the RX buffer parameters (xfer->rxd and xfer->rxcnt), the new unified helper introduces a 'response' boolean. All updated PMIC call sites now explicitly pass 'true' for this argument. This ensures the unified helper takes the 'if (response)' branch, performing the exact same assignments and preserving the original PMIC behavior. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260515-acpm-tmu-helpers-v2-1-8ca011d5a965@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-05-29RDMA/rxe: Fix typos in commentsPurushothaman Ramalingam
Fix typos found by codespell in driver comments: rxe.c: s/mangagement/management/ rxe_param.h: s/interations/iterations/ rxe_resp.c: s/recive/receive/ No functional change. Link: https://patch.msgid.link/r/20260527104527.3222-1-purush.ramalingam@gmail.com Signed-off-by: Purushothaman Ramalingam <purush.ramalingam@gmail.com> Reviewed-by: Zhu Yanjun <yanjun.zhu@linux.dev> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2026-05-29mmc: dw_mmc: Add desc_num field for clarityShawn Lin
The ring_size field in struct dw_mci is misleadingly named. Despite its name, it does not represent the size of the descriptor ring buffer in bytes, but rather the number of descriptors allocated within the fixed-size ring buffer. The actual ring buffer size is fixed at PAGE_SIZE (or DESC_RING_BUF_SZ, which equals PAGE_SIZE). Within this buffer, we allocate either struct idmac_desc or struct idmac_desc_64addr descriptors, and ring_size stores the count of these descriptors. This naming has caused confusion, as it's also used to set mmc->max_segs (the maximum number of scatter-gather segments), which logically corresponds to the number of descriptors, not a size in bytes. No functional change is introduced by this naming-only patch. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29mmc: sdhci: add signal voltage switch in sdhci_resume_hostJisheng Zhang
I met one suspend/resume issue with sdr104 capable sdio wifi card (with "keep-power-in-suspend" set in DT property): After resuming from suspend to ram, the sdio wifi card stops working. Further debug shows that although ios shows the sdio card is at sdr104 mode, the voltage is still at 3V3. This is due to missing the calling of ->start_signal_voltage_switch() in sdhci_resume_host(). Fix this issue by adding ->start_signal_voltage_switch() in sdhci_resume_host(). This also matches what we do for sdhci_runtime_resume_host(). Then the question is: why this issue hasn't reported and fixed for so long time. IMHO, several reasons: Some host controllers just kick off the runtime resume for system resume, so they benefit from the well supported runtime pm code; Some platforms just use the old sdio wifi card which doesn't need signal voltage switch at all, the default voltage is 3v3 after resuming. Fixes: 6308d2905bd3 ("mmc: sdhci: add quirk for keeping card power during suspend") Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29mmc: dw_mmc-rockchip: Add missing private data for very old controllersHeiko Stuebner
The really old controllers (rk2928, rk3066, rk3188) do not support UHS speeds at all, and thus never handled phase data. For that reason it never had a parse_dt callback and no driver private data at all. Commit ff6f0286c896 ("mmc: dw_mmc-rockchip: Add memory clock auto-gating support") makes the private data sort of mandatory, because the init function checks whether phases are configured internally or through the clock controller. This results in the old SoCs then experiencing NULL-pointer dereferences when they try to access that private-data struct. While we could have if (priv) conditionals in all places, it's way less cluttery to just give the old types their private-data struct. Fixes: ff6f0286c896 ("mmc: dw_mmc-rockchip: Add memory clock auto-gating support") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29mmc: sdhci-of-dwcmshc: use dev_err_probe() to simplify error pathsArtem Shimko
Replace common pattern of dev_err() + return with dev_err_probe() in probe functions and their callees. This macro provides standardized error message format with symbolic error names and adds deferred probe debugging information. The conversion makes the code more compact and ensures consistent error logging across all initialization paths. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Artem Shimko <a.shimko.dev@gmail.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29mmc: sdhci-of-dwcmshc: remove redundant IS_ERR() checkArtem Shimko
The clk_disable_unprepare() function has internal protection against ERR_PTR and NULL pointers (IS_ERR_OR_NULL). Remove the redundant IS_ERR() check for bus_clk in dwcmshc_suspend() and in the error path of dwcmshc_resume() to simplify the code. Note that the clk_prepare_enable() call in dwcmshc_resume() must retain its IS_ERR() check because clk_prepare() only handles NULL pointers, not ERR_PTR. No functional change intended. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Artem Shimko <a.shimko.dev@gmail.com> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29Merge branch 'acpi-driver-devm'Rafael J. Wysocki
Merge updates that introduce devm_acpi_install_notify_handler() and convert some drivers for core ACPI devices previously using acpi_dev_install_notify_handler() to devres-based resource management. * acpi-driver-devm: ACPI: video: Switch over to devres-based resource management ACPI: video: Use devm for video->entry and backlight cleanup ACPI: video: Use devm action for freeing video devices ACPI: video: Use devm action for video bus object cleanup ACPI: video: Rearrange probe and remove code ACPI: video: Reduce the number of auxiliary device dereferences ACPI: PAD: Switch over to devres-based resource management ACPI: PAD: Fix teardown ordering in acpi_pad_remove() ACPI: PAD: Pass struct device pointer to acpi_pad_notify() ACPI: PAD: Rearrange acpi_pad_notify() ACPI: thermal: Switch over to devres-based resource management ACPI: HED: Switch over to devres-based resource management ACPI: HED: Refine guarding against adding a second instance ACPI: battery: Switch over to devres-based resource management ACPI: AC: Switch over to devres-based resource management ACPI: NFIT: core: Use devm_acpi_install_notify_handler() ACPI: bus: Introduce devm_acpi_install_notify_handler()
2026-05-29mmc: litex_mmc: Set mandatory idle clocks before CMD0Inochi Amaoto
The litex_mmc driver assumes the card is already probed in the BIOS and skip the phy initialization. This will cause the command fail like the following when the old card is unplugged and then insert a new card: [ 62.923593] litex-mmc f0004000.mmc: Command (cmd 8) error, status -110 [ 62.949717] litex-mmc f0004000.mmc: Command (cmd 55) error, status -110 [ 62.976606] litex-mmc f0004000.mmc: Command (cmd 55) error, status -110 [ 63.002516] litex-mmc f0004000.mmc: Command (cmd 55) error, status -110 [ 63.028442] litex-mmc f0004000.mmc: Command (cmd 55) error, status -110 Add required clock settings and initialization for the CMD 0, so it can probe the new card. Fixes: 92e099104729 ("mmc: Add driver for LiteX's LiteSDCard interface") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Gabriel Somlo <gsomlo@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulfh@kernel.org>
2026-05-29Merge branch 'acpi-pmic'Rafael J. Wysocki
Merge an ACPI PMIC driver cleanup for 7.2. * acpi-pmic: ACPI: PMIC: Replace mutex_lock/unlock() with guard()/scoped_guard()