From 6ab3581ab19fa348b93c85a793e45cd8a80912a8 Mon Sep 17 00:00:00 2001 From: Clément Le Goffic Date: Tue, 18 Nov 2025 16:07:59 +0100 Subject: dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LPDDR, DDR and so SDRAM channels exist and share the same properties, they have a compatible, ranks, and an io-width. Signed-off-by: Clément Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Clément Le Goffic Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-3-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr-channel.yaml | 146 -------------------- .../ddr/jedec,sdram-channel.yaml | 147 +++++++++++++++++++++ 2 files changed, 147 insertions(+), 146 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml deleted file mode 100644 index 34b5bd153f63..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml +++ /dev/null @@ -1,146 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: LPDDR channel with chip/rank topology description - -description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, including the - amount of individual LPDDR chips and the ranks per chip. - -maintainers: - - Julius Werner - -properties: - compatible: - enum: - - jedec,lpddr2-channel - - jedec,lpddr3-channel - - jedec,lpddr4-channel - - jedec,lpddr5-channel - - io-width: - description: - The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that - multiple instances of that type of chip are wired in parallel on this - channel (with the channel's DQ pins split up between the different - chips, and the CA, CS, etc. pins of the different chips all shorted - together). This means that the total physical memory controlled by a - channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. - enum: - - 8 - - 16 - - 32 - - 64 - - 128 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - -patternProperties: - "^rank@[0-9]+$": - type: object - description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus - transaction on the channel targets exactly one rank, based on the - state of the CS pins. Different ranks may have different densities and - timing requirements. - required: - - reg - -allOf: - - if: - properties: - compatible: - contains: - const: jedec,lpddr2-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr3-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr4-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr5-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# - -required: - - compatible - - io-width - - "#address-cells" - - "#size-cells" - -additionalProperties: false - -examples: - - | - lpddr-channel0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "jedec,lpddr3-channel"; - io-width = <32>; - - rank@0 { - compatible = "lpddr3-ff,0100", "jedec,lpddr3"; - reg = <0>; - density = <8192>; - io-width = <16>; - revision-id = <1 0>; - }; - }; - - lpddr-channel1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "jedec,lpddr4-channel"; - io-width = <32>; - - rank@0 { - compatible = "lpddr4-05,0301", "jedec,lpddr4"; - reg = <0>; - density = <4096>; - io-width = <32>; - revision-id = <3 1>; - }; - - rank@1 { - compatible = "lpddr4-05,0301", "jedec,lpddr4"; - reg = <1>; - density = <2048>; - io-width = <32>; - revision-id = <3 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml new file mode 100644 index 000000000000..9892da520fe4 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDRAM channel with chip/rank topology description + +description: + A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely + independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory + chips to a host system. The main purpose of this node is to overall memory + topology of the system, including the amount of individual memory chips and + the ranks per chip. + +maintainers: + - Julius Werner + +properties: + compatible: + enum: + - jedec,lpddr2-channel + - jedec,lpddr3-channel + - jedec,lpddr4-channel + - jedec,lpddr5-channel + + io-width: + description: + The number of DQ pins in the channel. If this number is different + from (a multiple of) the io-width of the SDRAM chip, that means that + multiple instances of that type of chip are wired in parallel on this + channel (with the channel's DQ pins split up between the different + chips, and the CA, CS, etc. pins of the different chips all shorted + together). This means that the total physical memory controlled by a + channel is equal to the sum of the densities of each rank on the + connected SDRAM chip, times the io-width of the channel divided by + the io-width of the SDRAM chip. + enum: + - 8 + - 16 + - 32 + - 64 + - 128 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^rank@[0-9]+$": + type: object + description: + Each physical SDRAM chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each SDRAM bus + transaction on the channel targets exactly one rank, based on the + state of the CS pins. Different ranks may have different densities and + timing requirements. + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: jedec,lpddr2-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr3-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr5-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# + +required: + - compatible + - io-width + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + lpddr-channel0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr3-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr3-ff,0100", "jedec,lpddr3"; + reg = <0>; + density = <8192>; + io-width = <16>; + revision-id = <1 0>; + }; + }; + + lpddr-channel1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr4-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <0>; + density = <4096>; + io-width = <32>; + revision-id = <3 1>; + }; + + rank@1 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <1>; + density = <2048>; + io-width = <32>; + revision-id = <3 1>; + }; + }; -- cgit v1.2.3