From 7556a55b07c05263c3a28eb527c9cd3f3186fcfe Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 9 May 2025 16:46:38 +0100 Subject: arm64: dts: fvp: Add system timer for broadcast during CPU idle Introduce a system-level timer node in the FVP device tree to act as a broadcast timer when CPUs are in context losing idle states where the local timer stops on entering such low power states. This change complements recent CPU idle state additions. Tested-by: Leo Yan Message-Id: <20250509154640.836093-1-sudeep.holla@arm.com> Reviewed-by: Liviu Dudau Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 9e10d7a6b5a2..50b5993a2460 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -217,6 +217,19 @@ ; }; + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + ranges = <0 0x0 0x2a820000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + frame@2a830000 { + frame-number = <1>; + interrupts = ; + reg = <0x10000 0x10000>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; -- cgit v1.2.3 From 44845ea83d5e144b746ad0b5b9976e7fd3a843f9 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 9 May 2025 16:46:39 +0100 Subject: arm64: dts: fvp: Add CPU idle states for Rev C model Add CPU idle state definitions to the FVP Rev C device tree to enable support for CPU lower power modes. This allows the system to properly enter low power states during idle. It is disabled by default as it is know to impact performance on the models. Note that the power_state parameter(arm,psci-suspend-param) doesn't use the Extended StateID format for compatibility reasons on FVP. Tested on the FVP Rev C model with PSCI support enabled firmware. Tested-by: Leo Yan Message-Id: <20250509154640.836093-2-sudeep.holla@arm.com> Reviewed-by: Liviu Dudau Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 50b5993a2460..755b1407c4dc 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -44,6 +44,30 @@ #address-cells = <2>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + status = "disabled"; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + status = "disabled"; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; @@ -56,6 +80,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { device_type = "cpu"; @@ -69,6 +94,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { device_type = "cpu"; @@ -82,6 +108,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { device_type = "cpu"; @@ -95,6 +122,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@10000 { device_type = "cpu"; @@ -108,6 +136,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu5: cpu@10100 { device_type = "cpu"; @@ -121,6 +150,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu6: cpu@10200 { device_type = "cpu"; @@ -134,6 +164,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu7: cpu@10300 { device_type = "cpu"; @@ -147,6 +178,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; C0_L2: l2-cache0 { compatible = "cache"; -- cgit v1.2.3 From bbb59b3614a7f0f5cbf4bfc5159c4e6ed81401cb Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 9 May 2025 16:46:40 +0100 Subject: arm64: dts: fvp: Reserve 64MB for the FF-A firmware in memory map Reserve 64MB of memory at the end of the first bank of DRAM on FVP model. This is mainly for FF-A firmware use, as required by various firmware configurations using the Firmware Framework for Arm (FF-A). This prevents the kernel from overwriting the firmware region. This is also useful when running other firmware configurations(non FF-A based) that rely on usage of 64MB at the end of first DRAM bank. Necessary for proper coexistence of firmware(FF-A partitions) and the OS. Message-Id: <20250509154640.836093-3-sudeep.holla@arm.com> Reviewed-by: Liviu Dudau Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 755b1407c4dc..a5024075e3f3 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -201,7 +201,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, + reg = <0x00000000 0x80000000 0 0x7c000000>, <0x00000008 0x80000000 0 0x80000000>; }; -- cgit v1.2.3 From 1fa3ed04ac55134063e3cd465b41aeb26715e52a Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 12 May 2025 11:11:32 +0100 Subject: arm64: dts: arm: Drop the clock-frequency property from timer nodes Drop the clock-frequency property from the timer nodes, since it must be configured by the boot/secure firmware. Cc: Liviu Dudau Cc: Lorenzo Pieralisi Cc: Mark Rutland Message-Id: <20250512101132.1743920-1-sudeep.holla@arm.com> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 - arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 - arch/arm64/boot/dts/arm/juno-base.dtsi | 1 - arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 56ada8728b60..f35a5c96f3da 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -109,7 +109,6 @@ reg = <0x1a220000 0x1000>; #address-cells = <1>; #size-cells = <1>; - clock-frequency = <50000000>; ranges; frame@1a230000 { diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 083be35495b3..a4b2b78d4df3 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -77,7 +77,6 @@ , , ; - clock-frequency = <100000000>; }; pmu { diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 055764d0b9e5..9ccb80821bdb 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -10,7 +10,6 @@ memtimer: timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x2a820000 0x20000>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index 7f7226711d4b..a4a29193d4eb 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -116,7 +116,6 @@ , , ; - clock-frequency = <100000000>; }; pmu { -- cgit v1.2.3 From 6332351622db251b97639817a0e9ebc6f2394f87 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 12 May 2025 16:11:49 +0100 Subject: arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model The FVP Rev C model includes CoreSight ETE and TRBE support. These features can be enabled by specifying parameters when launching the model: | -C cluster0.has_ete: 1 | -C cluster1.has_ete: 1 | -C cluster0.has_trbe: 1 | -C cluster1.has_trbe: 1 This change adds device tree nodes for the ETE and TRBE. They are disabled by default to prevent kernel warnings from failed driver probes, as the model does not enable the features unless explicitly specified as mentioned above. Signed-off-by: Leo Yan Message-Id: <20250512151149.13111-1-leo.yan@arm.com> Acked-by: Suzuki K Poulose Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 54 +++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index a5024075e3f3..68a69f17e93d 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -272,6 +272,60 @@ interrupts = ; }; + ete-0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu0>; + status = "disabled"; + }; + + ete-1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu1>; + status = "disabled"; + }; + + ete-2 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu2>; + status = "disabled"; + }; + + ete-3 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu3>; + status = "disabled"; + }; + + ete-4 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu4>; + status = "disabled"; + }; + + ete-5 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu5>; + status = "disabled"; + }; + + ete-6 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu6>; + status = "disabled"; + }; + + ete-7 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu7>; + status = "disabled"; + }; + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = ; + status = "disabled"; + }; + pci: pci@40000000 { #address-cells = <0x3>; #size-cells = <0x2>; -- cgit v1.2.3