From 0f90f883b340402e44ee2a9fa9f75ecb7c075a4f Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 5 May 2026 16:41:11 +0000 Subject: dt-bindings: interconnect: document the RPM Network-On-Chip interconnect in Shikra SoC Document the RPM Network-On-Chip Interconnect for the Qualcomm Shikra platform. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Raviteja Laggyshetty Link: https://patch.msgid.link/20260505-shikra_icc-v3-1-8e03ff27c007@oss.qualcomm.com Signed-off-by: Georgi Djakov --- include/dt-bindings/interconnect/qcom,shikra.h | 121 +++++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,shikra.h (limited to 'include') diff --git a/include/dt-bindings/interconnect/qcom,shikra.h b/include/dt-bindings/interconnect/qcom,shikra.h new file mode 100644 index 000000000000..a42ea22ee162 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,shikra.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H + +#define MASTER_QUP_CORE_0 0 +#define SLAVE_QUP_CORE_0 1 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_AHB2PHY_USB 2 +#define SLAVE_APSS_THROTTLE_CFG 3 +#define SLAVE_AUDIO 4 +#define SLAVE_BOOT_ROM 5 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CDSP_THROTTLE_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_DSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MX_CFG 12 +#define SLAVE_CRYPTO_0_CFG 13 +#define SLAVE_DDR_SS_CFG 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_EMAC0_CFG 16 +#define SLAVE_EMAC1_CFG 17 +#define SLAVE_GPU_CFG 18 +#define SLAVE_GPU_THROTTLE_CFG 19 +#define SLAVE_HWKM 20 +#define SLAVE_IMEM_CFG 21 +#define SLAVE_MAPSS 22 +#define SLAVE_MDSP_MPU_CFG 23 +#define SLAVE_MESSAGE_RAM 24 +#define SLAVE_MSS 25 +#define SLAVE_PCIE_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PKA_WRAPPER_CFG 29 +#define SLAVE_PMIC_ARB 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QM_CFG 32 +#define SLAVE_QM_MPU_CFG 33 +#define SLAVE_QPIC 34 +#define SLAVE_QUP_0 35 +#define SLAVE_RPM 36 +#define SLAVE_SDCC_1 37 +#define SLAVE_SDCC_2 38 +#define SLAVE_SECURITY 39 +#define SLAVE_SNOC_CFG 40 +#define SNOC_SF_THROTTLE_CFG 41 +#define SLAVE_TLMM 42 +#define SLAVE_TSCSS 43 +#define SLAVE_USB2 44 +#define SLAVE_USB3 45 +#define SLAVE_VENUS_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_SERVICE_CNOC 49 + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_GRAPHICS_3D 0 +#define MASTER_MNOC_HF_MEM_NOC 1 +#define MASTER_ANOC_PCIE_MEM_NOC 2 +#define MASTER_SNOC_SF_MEM_NOC 3 +#define MASTER_AMPSS_M0 4 +#define MASTER_SYS_TCU 5 +#define SLAVE_LLCC 6 +#define SLAVE_MEMNOC_SNOC 7 +#define SLAVE_MEM_NOC_PCIE_SNOC 8 + +#define MASTER_CAMNOC_SF 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define SLAVE_MMNRT_VIRT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP_PORT0 1 +#define MASTER_MMRT_VIRT 2 +#define SLAVE_MM_MEMNOC 3 + +#define MASTER_SNOC_CFG 0 +#define MASTER_TIC 1 +#define MASTER_ANOC_SNOC 2 +#define MASTER_MEMNOC_PCIE 3 +#define MASTER_MEMNOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_PCIE2_0 6 +#define MASTER_QDSS_BAM 7 +#define MASTER_QPIC 8 +#define MASTER_QUP_0 9 +#define CNOC_SNOC_MAS 10 +#define MASTER_AUDIO 11 +#define MASTER_EMAC_0 12 +#define MASTER_EMAC_1 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_1 15 +#define MASTER_SDCC_2 16 +#define MASTER_USB2_0 17 +#define MASTER_USB3 18 +#define MASTER_CRYPTO_CORE0 19 +#define SLAVE_APPSS 20 +#define SLAVE_MCUSS 21 +#define SLAVE_WCSS 22 +#define SLAVE_MEMNOC_SF 23 +#define SNOC_CNOC_SLV 24 +#define SLAVE_BOOTIMEM 25 +#define SLAVE_OCIMEM 26 +#define SLAVE_PIMEM 27 +#define SLAVE_SERVICE_SNOC 28 +#define SLAVE_PCIE2_0 29 +#define SLAVE_QDSS_STM 30 +#define SLAVE_TCU 31 +#define SLAVE_PCIE_MEMNOC 32 +#define SLAVE_ANOC_SNOC 33 + +#endif -- cgit v1.2.3 From 8d315860b5cce17559151d04b1d85022f0bb15a2 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 10 May 2026 10:06:06 +0800 Subject: dt-bindings: interconnect: Document RPMh Network-On-Chip for Qualcomm Nord SoC Add RPMh Network-On-Chip interconnect bindings for Qualcomm Nord SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo Link: https://patch.msgid.link/20260510020607.1129773-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,nord-rpmh.yaml | 131 +++++++++++++ include/dt-bindings/interconnect/qcom,nord-rpmh.h | 217 +++++++++++++++++++++ 2 files changed, 348 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,nord-rpmh.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml new file mode 100644 index 000000000000..3650d3d5b918 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,nord-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Nord + +maintainers: + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,nord-rpmh.h + +properties: + compatible: + enum: + - qcom,nord-aggre1-noc + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + - qcom,nord-aggre2-noc-tile + - qcom,nord-clk-virt + - qcom,nord-cnoc-cfg + - qcom,nord-cnoc-main + - qcom,nord-hpass-ag-noc + - qcom,nord-hscnoc + - qcom,nord-mc-virt + - qcom,nord-mmss-noc + - qcom,nord-nsp-data-noc-0 + - qcom,nord-nsp-data-noc-1 + - qcom,nord-nsp-data-noc-2 + - qcom,nord-nsp-data-noc-3 + - qcom,nord-pcie-cfg + - qcom,nord-pcie-data-inbound + - qcom,nord-pcie-data-outbound + - qcom,nord-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-clk-virt + - qcom,nord-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB2 AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-clk-virt { + compatible = "qcom,nord-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible = "qcom,nord-aggre1-noc-tile"; + reg = <0x01720000 0x23400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&ne_gcc_aggre_noc_ufs_phy_axi_clk>, + <&ne_gcc_aggre_noc_usb2_axi_clk>, + <&ne_gcc_aggre_noc_usb3_prim_axi_clk>, + <&ne_gcc_aggre_noc_usb3_sec_axi_clk>; + }; diff --git a/include/dt-bindings/interconnect/qcom,nord-rpmh.h b/include/dt-bindings/interconnect/qcom,nord-rpmh.h new file mode 100644 index 000000000000..5bdce6a9bab7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,nord-rpmh.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H + +#define MASTER_QSPI_0 0 +#define MASTER_SAILSS_MD1 1 +#define MASTER_QUP_3 2 +#define SLAVE_A1NOC_SNOC 3 + +#define MASTER_QUP_2 0 +#define MASTER_CRYPTO_CORE0 1 +#define MASTER_CRYPTO_CORE1 2 +#define MASTER_CRYPTO_CORE2 3 +#define MASTER_SDCC_4 4 +#define MASTER_UFS_MEM 5 +#define MASTER_USB2 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A1NOC_HSCNOC 9 + +#define MASTER_IPA 0 +#define MASTER_SOCCP_AGGR_NOC 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_QDSS_ETR_1 3 +#define SLAVE_A2NOC_SNOC 4 + +#define MASTER_QUP_0 0 +#define MASTER_QUP_1 1 +#define MASTER_EMAC_0 2 +#define MASTER_EMAC_1 3 +#define SLAVE_A2NOC_HSCNOC 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_PS_ETH_0 1 +#define SLAVE_PS_ETH_1 2 +#define SLAVE_SHS_SERVER 3 +#define SLAVE_AHB2PHY_0 4 +#define SLAVE_AHB2PHY_1 5 +#define SLAVE_AHB2PHY_2 6 +#define SLAVE_AHB2PHY_3 7 +#define SLAVE_AHB2PHY_ETH_0 8 +#define SLAVE_AHB2PHY_ETH_1 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_CRYPTO_1_CFG 13 +#define SLAVE_CRYPTO_2_CFG 14 +#define SLAVE_DISPLAY_1_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_DPRX0 17 +#define SLAVE_DPRX1 18 +#define SLAVE_EVA_CFG 19 +#define SLAVE_GFX3D_CFG 20 +#define SLAVE_GFX3D_1_CFG 21 +#define SLAVE_I2C 22 +#define SLAVE_IMEM_CFG 23 +#define SLAVE_MCW_PCIE 24 +#define SLAVE_MM_RSCC 25 +#define SLAVE_NE_CLK_CTL 26 +#define SLAVE_NSPSS0_CFG 27 +#define SLAVE_NSPSS1_CFG 28 +#define SLAVE_NSPSS2_CFG 29 +#define SLAVE_NSPSS3_CFG 30 +#define SLAVE_NW_CLK_CTL 31 +#define SLAVE_PRNG 32 +#define SLAVE_QDSS_CFG 33 +#define SLAVE_QSPI_0 34 +#define SLAVE_QUP_0 35 +#define SLAVE_QUP_3 36 +#define SLAVE_QUP_1 37 +#define SLAVE_QUP_2 38 +#define SLAVE_SAFEDMA_CFG 39 +#define SLAVE_SDCC_4 40 +#define SLAVE_SE_CLK_CTL 41 +#define SLAVE_TCSR 42 +#define SLAVE_TLMM 43 +#define SLAVE_TSC_CFG 44 +#define SLAVE_UFS_MEM_CFG 45 +#define SLAVE_USB2 46 +#define SLAVE_USB3_0 47 +#define SLAVE_USB3_1 48 +#define SLAVE_VENUS_CFG 49 +#define SLAVE_COMPUTENOC_CFG 50 +#define SLAVE_PCIE_NOC_CFG 51 +#define SLAVE_QTC_CFG 52 +#define SLAVE_QDSS_STM 53 +#define SLAVE_SYS_TCU0_CFG 54 +#define SLAVE_SYS_TCU1_CFG 55 +#define SLAVE_SYS_TCU2_CFG 56 + +#define MASTER_MM_RSCC 0 +#define MASTER_HSCNOC_CNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_HBCU 3 +#define SLAVE_IPA_CFG 4 +#define SLAVE_IPC_ROUTER_CFG 5 +#define SLAVE_SOCCP 6 +#define SLAVE_TME_CFG 7 +#define SLAVE_PCIE_DMA 8 +#define SLAVE_CNOC_CFG 9 +#define SLAVE_DDRSS_CFG 10 +#define SLAVE_IMEM 11 + +#define MASTER_HPASS_PROC_0 0 +#define MASTER_HPASS_PROC_1 1 +#define MASTER_HPASS_PROC_2 2 +#define SLAVE_HPASS_AGNOC_AUDIO 3 + +#define MASTER_GPU_TCU 0 +#define MASTER_QTC_TCU 1 +#define MASTER_SYS_TCU_0 2 +#define MASTER_SYS_TCU_1 3 +#define MASTER_SYS_TCU_2 4 +#define MASTER_APPSS_PROC 5 +#define MASTER_A1NOC_TILE_HSCNOC 6 +#define MASTER_A2NOC_TILE_HSCNOC 7 +#define MASTER_GFX3D 8 +#define MASTER_GFX3D_1 9 +#define MASTER_HPASS_ADAS_HSCNOC 10 +#define MASTER_HPASS_AUDIO_HSCNOC 11 +#define MASTER_MNOC_HF_MEM_NOC 12 +#define MASTER_MNOC_SF_MEM_NOC 13 +#define MASTER_NSP0_HSCNOC 14 +#define MASTER_NSP1_HSCNOC 15 +#define MASTER_NSP2_HSCNOC 16 +#define MASTER_NSP3_HSCNOC 17 +#define MASTER_ANOC_PCIE_GEM_NOC 18 +#define MASTER_SAILSS_MD0_HSCNOC 19 +#define MASTER_SNOC_SF_MEM_NOC 20 +#define MASTER_GIC 21 +#define SLAVE_HSCNOC_CNOC 22 +#define SLAVE_LLCC 23 +#define SLAVE_MEM_NOC_PCIE_SNOC 24 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_DPRX0 4 +#define MASTER_DPRX1 5 +#define MASTER_MDP0 6 +#define MASTER_MDP1 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_EVA 9 +#define MASTER_VIDEO_MVP0 10 +#define MASTER_VIDEO_MVP1 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 + +#define MASTER_NSP0_PROC 0 +#define SLAVE_NSP0_HSC_NOC 1 + +#define MASTER_NSP1_PROC 0 +#define SLAVE_NSP1_HSC_NOC 1 + +#define MASTER_NSP2_PROC 0 +#define SLAVE_NSP2_HSC_NOC 1 + +#define MASTER_NSP3_PROC 0 +#define SLAVE_NSP3_HSC_NOC 1 + +#define MASTER_PCIE_NOC_CFG 0 +#define SLAVE_PCIE_AHB2PHY_CFG 1 +#define SLAVE_PCIE_CFG_0 2 +#define SLAVE_PCIE_CFG_1 3 +#define SLAVE_PCIE_CFG_2 4 +#define SLAVE_PCIE_CFG_3 5 +#define SLAVE_PCIE_DMA_0_CFG 6 +#define SLAVE_PCIE_DMA_1_CFG 7 +#define SLAVE_PCIE_DMA_2_CFG 8 + +#define MASTER_PCIE_DMA_0 0 +#define MASTER_PCIE_DMA_1 1 +#define MASTER_PCIE_DMA_2 2 +#define MASTER_PCIE_0 3 +#define MASTER_PCIE_1 4 +#define MASTER_PCIE_2 5 +#define MASTER_PCIE_3 6 +#define SLAVE_PCIE_HSCNOC 7 +#define SLAVE_PCIE_OBNOC_DMA 8 + +#define MASTER_CNOC_PCIE_DMA 0 +#define MASTER_ANOC_PCIE_HSCNOC 1 +#define MASTER_PCIE_IBNOC_DMA 2 +#define SLAVE_PCIE_DMA_0 3 +#define SLAVE_PCIE_DMA_1 4 +#define SLAVE_PCIE_DMA_2 5 +#define SLAVE_PCIE_0 6 +#define SLAVE_PCIE_1 7 +#define SLAVE_PCIE_2 8 +#define SLAVE_PCIE_3 9 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_CNOC_SNOC 2 +#define MASTER_NSINOC_SNOC 3 +#define MASTER_SAFE_DMA 4 +#define SLAVE_SNOC_HSCNOC_SF 5 + +#endif -- cgit v1.2.3 From 8549642259cdb405e9815c4d55a7bb32114d42e6 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 14 May 2026 16:36:23 +0300 Subject: dt-bindings: interconnect: qcom,eliza-rpmh: Add SDCC1 slave The Eliza RPMh interconnect binding is missing the SDCC1 CNOC CFG slave ID. Add it so SDCC1 consumer can describe the corresponding interconnect path. Append the new ID to preserve the existing ABI values. Signed-off-by: Abel Vesa Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260514-eliza-interconnect-add-missing-sdcc1-slave-node-v2-1-13c03bc890cb@oss.qualcomm.com Signed-off-by: Georgi Djakov --- include/dt-bindings/interconnect/qcom,eliza-rpmh.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/interconnect/qcom,eliza-rpmh.h b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h index 95db2fe647de..dfe99feefb27 100644 --- a/include/dt-bindings/interconnect/qcom,eliza-rpmh.h +++ b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h @@ -57,6 +57,7 @@ #define SLAVE_PCIE_ANOC_CFG 27 #define SLAVE_QDSS_STM 28 #define SLAVE_TCU 29 +#define SLAVE_SDCC_1 30 #define MASTER_GEM_NOC_CNOC 0 #define MASTER_GEM_NOC_PCIE_SNOC 1 -- cgit v1.2.3 From 07548b04dc36678898f1d1274c2e1731ce264701 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Wed, 6 May 2026 11:38:46 -0700 Subject: dt-bindings: interconnect: qcom: document the RPMh NoC for Hawi SoC Document the RPMh Network-On-Chip interconnect for the Qualcomm Hawi SoC. Reviewed-by: Mike Tipton Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vivek Aknurwar Link: https://patch.msgid.link/20260506-icc-hawi-v4-1-35447fdc482b@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,hawi-rpmh.yaml | 131 ++++++++++++++++ include/dt-bindings/interconnect/qcom,hawi-rpmh.h | 165 +++++++++++++++++++++ 2 files changed, 296 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,hawi-rpmh.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml new file mode 100644 index 000000000000..49a2dca5db62 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi + +maintainers: + - Vivek Aknurwar + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h + +properties: + compatible: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-clk-virt + - qcom,hawi-cnoc-main + - qcom,hawi-gem-noc + - qcom,hawi-llclpi-noc + - qcom,hawi-lpass-ag-noc + - qcom,hawi-lpass-lpiaon-noc + - qcom,hawi-lpass-lpicx-noc + - qcom,hawi-mc-virt + - qcom,hawi-mmss-noc + - qcom,hawi-nsp-noc + - qcom,hawi-pcie-anoc + - qcom,hawi-stdst-cfg + - qcom,hawi-stdst-main + - qcom,hawi-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-clk-virt + - qcom,hawi-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clk_virt: interconnect-0 { + compatible = "qcom,hawi-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible = "qcom,hawi-aggre1-noc"; + reg = <0x0 0xf00000 0x0 0x54400>; + #interconnect-cells = <2>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,hawi-rpmh.h b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h new file mode 100644 index 000000000000..a8b649679846 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,hawi-rpmh.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_HAWI_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_2 1 +#define MASTER_QUP_3 2 +#define MASTER_QUP_4 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_QUP_1 6 +#define MASTER_SOCCP_PROC 7 +#define MASTER_QDSS_ETR 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_SDCC_2 10 +#define MASTER_SDCC_4 11 +#define MASTER_UFS_MEM 12 +#define MASTER_USB3 13 +#define SLAVE_A1NOC_SNOC 14 + +#define MASTER_DDR_EFF_VETO 0 +#define MASTER_QUP_CORE_0 1 +#define MASTER_QUP_CORE_1 2 +#define MASTER_QUP_CORE_2 3 +#define MASTER_QUP_CORE_3 4 +#define MASTER_QUP_CORE_4 5 +#define SLAVE_DDR_EFF_VETO 6 +#define SLAVE_QUP_CORE_0 7 +#define SLAVE_QUP_CORE_1 8 +#define SLAVE_QUP_CORE_2 9 +#define SLAVE_QUP_CORE_3 10 +#define SLAVE_QUP_CORE_4 11 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_FENCE 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_CNOC_CFG 7 +#define SLAVE_DDRSS_CFG 8 +#define SLAVE_IMEM 9 +#define SLAVE_PCIE_0 10 +#define SLAVE_PCIE_1 11 + +#define MASTER_GIC 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_GFX3D 4 +#define MASTER_LPASS_GEM_NOC 5 +#define MASTER_MSS_PROC 6 +#define MASTER_MNOC_HF_MEM_NOC 7 +#define MASTER_MNOC_SF_MEM_NOC 8 +#define MASTER_COMPUTE_NOC 9 +#define MASTER_ANOC_PCIE_GEM_NOC 10 +#define MASTER_QPACE 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define MASTER_WLAN_Q6 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC_LLCLPI_NOC 0 +#define SLAVE_LPASS_LPI_CC 1 +#define SLAVE_LLCC_ISLAND 2 +#define SLAVE_SERVICE_LLCLPI_NOC 3 +#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define MASTER_DDR_RT 1 +#define SLAVE_EBI1 2 +#define SLAVE_DDR_RT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_MDSS_DCP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO_CV_PROC 7 +#define MASTER_VIDEO_EVA 8 +#define MASTER_VIDEO_MVP 9 +#define MASTER_VIDEO_V_PROC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_CFG_CENTER 0 +#define MASTER_CFG_EAST 1 +#define MASTER_CFG_MM 2 +#define MASTER_CFG_NORTH 3 +#define MASTER_CFG_SOUTH 4 +#define MASTER_CFG_SOUTHWEST 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_BOOT_ROM 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CRYPTO_CFG 10 +#define SLAVE_DISPLAY_CFG 11 +#define SLAVE_EVA_CFG 12 +#define SLAVE_GFX3D_CFG 13 +#define SLAVE_I2C 14 +#define SLAVE_IMEM_CFG 15 +#define SLAVE_IPC_ROUTER_CFG 16 +#define SLAVE_IRIS_CFG 17 +#define SLAVE_CNOC_MSS 18 +#define SLAVE_PCIE_0_CFG 19 +#define SLAVE_PCIE_1_CFG 20 +#define SLAVE_PRNG 21 +#define SLAVE_QSPI_0 22 +#define SLAVE_QUP_1 23 +#define SLAVE_QUP_2 24 +#define SLAVE_QUP_3 25 +#define SLAVE_QUP_4 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SDCC_4 28 +#define SLAVE_TLMM 29 +#define SLAVE_UFS_MEM_CFG 30 +#define SLAVE_USB3 31 +#define SLAVE_VSENSE_CTRL_CFG 32 +#define SLAVE_PCIE_ANOC_CFG 33 +#define SLAVE_QDSS_CFG 34 +#define SLAVE_QDSS_STM 35 +#define SLAVE_TCSR 36 +#define SLAVE_TCU 37 + +#define MASTER_CNOC_STARDUST 0 +#define SLAVE_STARDUST_CENTER_CFG 1 +#define SLAVE_STARDUST_EAST_CFG 2 +#define SLAVE_STARDUST_MM_CFG 3 +#define SLAVE_STARDUST_NORTH_CFG 4 +#define SLAVE_STARDUST_SOUTH_CFG 5 +#define SLAVE_STARDUST_SOUTHWEST_CFG 6 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_APSS_NOC 1 +#define MASTER_CNOC_SNOC 2 +#define SLAVE_SNOC_GEM_NOC_SF 3 + +#endif -- cgit v1.2.3