<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git, branch master</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/'/>
<updated>2026-07-01T16:00:24+00:00</updated>
<entry>
<title>lib: utils/mpxy: Add RPMI MPXY driver for logging service group</title>
<updated>2026-07-01T16:00:24+00:00</updated>
<author>
<name>Subrahmanya Lingappa</name>
<email>subrahmanya.lingappa@oss.qualcomm.com</email>
</author>
<published>2026-06-19T10:34:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=262571217c75c649115633d8075cb6a40d940733'/>
<id>urn:sha1:262571217c75c649115633d8075cb6a40d940733</id>
<content type='text'>
Add RPMI MPXY proxy driver for LOGGING service group so that
S-mode can leverage LOGGING service group implemented by the
platform microcontroller.

Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Signed-off-by: Subrahmanya Lingappa &lt;subrahmanya.lingappa@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: Bump-up version to 1.9</title>
<updated>2026-06-30T14:19:54+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup@brainfault.org</email>
</author>
<published>2026-06-30T14:19:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=cbf9f6734dd85a982c63e3cb5db7ffe09da839ca'/>
<id>urn:sha1:cbf9f6734dd85a982c63e3cb5db7ffe09da839ca</id>
<content type='text'>
Update the OpenSBI version to 1.9 as part of release preparation.

Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Fix comment after relocation completion</title>
<updated>2026-06-28T08:38:14+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2026-06-26T02:21:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=bf10d3bf89c05cbc4e266de8c9aff7eb55aee748'/>
<id>urn:sha1:bf10d3bf89c05cbc4e266de8c9aff7eb55aee748</id>
<content type='text'>
After relocation is done, the code is running from the load address,
not the link address. Fix the comment to correctly reflect this.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260626022121.1885209-1-zong.li@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_pmu: fix integer overflow in pmu_ctr_idx_validate</title>
<updated>2026-06-28T08:34:17+00:00</updated>
<author>
<name>liutong</name>
<email>liutong@iscas.ac.cn</email>
</author>
<published>2026-06-28T08:25:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=0dfe6be08778102bf2fde61c5c99ea2cceb0b73a'/>
<id>urn:sha1:0dfe6be08778102bf2fde61c5c99ea2cceb0b73a</id>
<content type='text'>
pmu_ctr_idx_validate() checks whether counter indices are in range
using cbase + sbi_fls(cmask) &lt; total_ctrs.  Both operands are unsigned
long, so a crafted cbase close to ULONG_MAX causes the addition to wrap
around to a small value that passes the comparison.

Once validation is bypassed, sbi_pmu_ctr_cfg_match() with the
SKIP_MATCH flag uses the overflowed index directly as an array subscript
into phs-&gt;active_events[], producing an out-of-bounds read in M-mode.
Through the firmware-event code path, the same overflowed index reaches
fw_counters_data[] and fw_counters_started, giving an attacker OOB
write-zero and OOB bit-set primitives in M-mode memory.

Fix pmu_ctr_idx_validate() by checking for unsigned overflow before the
comparison, and add a secondary bounds check on cidx_first in the
SKIP_MATCH path so that even if validation is somehow bypassed in the
future, the array access remains bounded.

Signed-off-by: liutong &lt;liutong@iscas.ac.cn&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260624035049.1753003-1-liutong@iscas.ac.cn
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: spacemit: k1: fix wrong address definitions</title>
<updated>2026-06-28T05:46:36+00:00</updated>
<author>
<name>Junhui Liu</name>
<email>junhui.liu@pigmoral.tech</email>
</author>
<published>2026-06-23T02:49:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=cc9b4ef8f3b465f4625ca40bf6af5e033df2bd75'/>
<id>urn:sha1:cc9b4ef8f3b465f4625ca40bf6af5e033df2bd75</id>
<content type='text'>
PMU_AP_CORE2_IDLE_CFG and PMU_AP_CORE3_IDLE_CFG are not continuous with
PMU_AP_CORE0_IDLE_CFG and PMU_AP_CORE1_IDLE_CFG. They are at PMU AP
base + 0x160 and + 0x164, matching the vendor OpenSBI definitions. After
fixing these addresses, the intermediate cluster offset macros are
redundant now, so define the wakeup and idle registers directly as
PMU_AP_BASE offsets. This makes the actual register addresses easier to
inspect and compare against the vendor code.

C1_RVBADDR_HI_ADDR is also corrected according to the vendor OpenSBI
definition. This was tested by writing an invalid value to the corrected
address, which prevents cluster1 CPUs from coming online, while doing
the same with the old address does not affect SMP boot.

Fixes: 1f84ec2a ("platform: generic: spacemit: add K1")
Signed-off-by: Junhui Liu &lt;junhui.liu@pigmoral.tech&gt;
Link: https://lore.kernel.org/r/20260623-k1-fix-addr-v1-1-3dbde8c03bd6@pigmoral.tech
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: mips eyeq7h: fix boot with JTAG</title>
<updated>2026-06-28T05:38:13+00:00</updated>
<author>
<name>Vladimir Kondratiev</name>
<email>vladimir.kondratiev@mobileye.com</email>
</author>
<published>2026-06-18T10:37:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=a2077d44cc5743b2fae084dd3cac9225e81bc2fb'/>
<id>urn:sha1:a2077d44cc5743b2fae084dd3cac9225e81bc2fb</id>
<content type='text'>
When JTAG is connected, internal logic leads to the bit
MIPS_CTL0_DBG_RST_DASRT (for the debug unit) stay high and
this prevents normal cluster power-up.

Force proper power-on reset value prior to power-up sequence.
Hold this value for about 10 usec

Signed-off-by: Vladimir Kondratiev &lt;vladimir.kondratiev@mobileye.com&gt;
Link: https://lore.kernel.org/r/20260618103713.2588984-1-vladimir.kondratiev@mobileye.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Rework misaligned vector load/store</title>
<updated>2026-06-17T06:13:38+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-09T06:00:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=a8be5e9478be08f09a720f7013ec30d6e2bd9fcc'/>
<id>urn:sha1:a8be5e9478be08f09a720f7013ec30d6e2bd9fcc</id>
<content type='text'>
Fix the following issues with misaligned vector load/store:

a. Stack overflow: the mask[VLEN_MAX / 8] variable consumes 8K stack
space, given VLEN_MAX=65536, overflowing the default-sized stack.
There's no need to fetch the whole mask in one go, instead, make it
on-demand. Use a 128-byte mask as local buffer to hold the sliding
window of mask. For rvv load, this is allowed -- from the spec:

  "The destination vector register group for a masked vector
   instruction cannot overlap the source mask register (v0),
   unless the destination vector register is being written with
   a mask value (e.g., compares) or the scalar result of a reduction"

We don't need to worry about the mask getting overwritten.

b. Maintain the value of vstart upon abort (uptrap) to avoid duplicate
work. After fault resolution, the instruction can restart from the
faulting vstart. For Fault-Only-First loads, reset vstart to 0, as
previously done so, to conform to spec.

c. Explicitly set VS dirty in VSSTATUS with SET_VS_DIRTY() if faulting
from V=1, and if any vector register, including vstart/vl/vtype, gets
changed in the handler. It can add 1 unnecessary op to set VS dirty
in M/SSTATUS (not VSSTATUS), where the HW already did, but for code
simplicity, do it anyway. The overhead should be negligible.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Tested-by: Anirudh Srinivasan &lt;asrinivasan@oss.tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260609060024.706-5-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add variable-length unprivilege access functions</title>
<updated>2026-06-17T06:11:11+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-09T06:00:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=914aeddaf16d91d39112056c5dd2b013b757a424'/>
<id>urn:sha1:914aeddaf16d91d39112056c5dd2b013b757a424</id>
<content type='text'>
sbi_load/store_loop read/write variable-length buffer unprivileged.
Both function use the widest aligned 8/4/2/1 byte load/stores in each
loop to reduce the total number of iterations.

Also switch the scalar/vector misaligned handlers to make use of such
functions to simplify code.

Miscellaneous: remove the unnecessary [taddr] in inline assembly

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Tested-by: Anirudh Srinivasan &lt;asrinivasan@oss.tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260609060024.706-4-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Rework and split sbi_misaligned(_v)_tinst_fixup</title>
<updated>2026-06-17T06:07:19+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-09T06:00:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=1475f147f646f337c85599b03bd3185fe591da39'/>
<id>urn:sha1:1475f147f646f337c85599b03bd3185fe591da39</id>
<content type='text'>
The load/store address offset between the uptrap and the orig_trap
can be derived by orig_trap-&gt;tval - uptrap-&gt;tval, thus refactor
the function prototype for simplicity.

For vector load, sbi_misaligned_v_tinst_fixup is introduced. There's
no transformed instruction for vector load/store, so null out tinst
if the fault is not a guest-page fault.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Tested-by: Anirudh Srinivasan &lt;asrinivasan@oss.tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260609060024.706-3-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: cosmetic changes to reduce indentation</title>
<updated>2026-06-17T05:53:05+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-09T06:00:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=4120e6dce250b3fcec44394dca528ee1f39f35ba'/>
<id>urn:sha1:4120e6dce250b3fcec44394dca528ee1f39f35ba</id>
<content type='text'>
In preparation for subsequent patches.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Tested-by: Anirudh Srinivasan &lt;asrinivasan@oss.tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260609060024.706-2-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
