<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git, branch release-1.5.x</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=release-1.5.x</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=release-1.5.x'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/'/>
<updated>2024-08-02T03:23:22+00:00</updated>
<entry>
<title>lib: sbi: check result of pmp_get() in is_pmp_entry_mapped()</title>
<updated>2024-08-02T03:23:22+00:00</updated>
<author>
<name>Carlos López</name>
<email>carlos.lopezr4096@gmail.com</email>
</author>
<published>2024-08-01T12:58:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=43cace6c3671e5172d0df0a8963e552bb04b7b20'/>
<id>urn:sha1:43cace6c3671e5172d0df0a8963e552bb04b7b20</id>
<content type='text'>
pmp_get() may return an error if the given entry, given by the caller
of is_pmp_entry_mapped(), is invalid. This results in the output
parameters for pmp_get() being uninitialized. To avoid using garbage
values, check the result and return early if necessary.

This issue is not being hit because at the moment
is_pmp_entry_mapped() is only being called from a single site with a
valid hardcoded value.

Signed-off-by: Carlos López &lt;carlos.lopezr4096@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: fwft: fix incorrect size passed to sbi_zalloc()</title>
<updated>2024-08-02T03:23:20+00:00</updated>
<author>
<name>Carlos López</name>
<email>carlos.lopezr4096@gmail.com</email>
</author>
<published>2024-08-01T12:48:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=cb0f4757fc2904cbf579e34feba891a5878625c5'/>
<id>urn:sha1:cb0f4757fc2904cbf579e34feba891a5878625c5</id>
<content type='text'>
The fwt_hart_state struct inciludes a flexible array member, so its
allocation size will be that of the struct itself, plus that of each
of the members in the array. When calculating this size, instead of
taking the size of the struct, the size of a pointer to it was taken,
which is incorrect. Luckily, this happenned to not produce memory
corruption because the size of the non-flexible members of the struct
is the same as the size of a pointer.

Signed-off-by: Carlos López &lt;carlos.lopezr4096@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: dbtr: fix potential NULL pointer dereferences</title>
<updated>2024-08-02T03:23:19+00:00</updated>
<author>
<name>Carlos López</name>
<email>carlos.lopezr4096@gmail.com</email>
</author>
<published>2024-08-01T12:27:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=baf6a75e3f967aa8b65a20963bd9ae21975ba75a'/>
<id>urn:sha1:baf6a75e3f967aa8b65a20963bd9ae21975ba75a</id>
<content type='text'>
In several dbtr functions, we first check that the dbtr trigger is not
NULL and that its state is what we expect. However, it only makes
sense to perform the second check if the dbtr trigger is not NULL.
Othwerwise we will dereference a NULL pointer. Thus, change the
condition so that it shortcuts to the first check if necessary.

Signed-off-by: Carlos López &lt;carlos.lopezr4096@gmail.com&gt;
Reviewed-By: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: Adjust Sscofpmf mhpmevent mask for upper 8 bits</title>
<updated>2024-08-02T03:23:17+00:00</updated>
<author>
<name>Eric Lin</name>
<email>eric.lin@sifive.com</email>
</author>
<published>2024-07-30T09:30:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=778949eeb8f36e01c37cb3ae6d82b0660a1bf6f7'/>
<id>urn:sha1:778949eeb8f36e01c37cb3ae6d82b0660a1bf6f7</id>
<content type='text'>
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for
the Sscofpmf extension.

However, according to the Sscofpmf extension specification[1],
it only defines the upper 8 bits in mhpmevent for privilege mode
inhibit and counter overflow disable. Other bits are defined by
the platform for event selection.

Since vendors might define raw event encoding exceeding 48 bits in
mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it.

Link: https://github.com/riscvarchive/riscv-count-overflow [1]
Signed-off-by: Eric Lin &lt;eric.lin@sifive.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_hsm: Save/restore menvcfg only when it exists</title>
<updated>2024-07-29T06:04:18+00:00</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-10T14:26:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=65a3938fadc537af178c84a349ade31ec6a70846'/>
<id>urn:sha1:65a3938fadc537af178c84a349ade31ec6a70846</id>
<content type='text'>
Attempting to access the menvcfg CSR raises an illegal instruction
exception on hardware which implements Sm1p11 or older.

Fixes: e9ee9678ba50 ("lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING")
Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: Bump-up version to 1.5</title>
<updated>2024-06-30T08:33:26+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-06-30T08:33:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=455de672dd7c2aa1992df54dfb08dc11abbc1b1a'/>
<id>urn:sha1:455de672dd7c2aa1992df54dfb08dc11abbc1b1a</id>
<content type='text'>
This patch updates OpenSBI version to 1.5 as part of
release preparation.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: check incoming dbtr shmem address</title>
<updated>2024-06-28T03:06:46+00:00</updated>
<author>
<name>Sergey Matyukevich</name>
<email>geomatsi@gmail.com</email>
</author>
<published>2024-06-27T12:04:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=23b7badeee3caa1445784273ba5dc8dbcbba7c34'/>
<id>urn:sha1:23b7badeee3caa1445784273ba5dc8dbcbba7c34</id>
<content type='text'>
Current Debug Trigger SBI extension proposal suggests to activate
shmem area and obtain its physical address from S-mode software
in the following way:

: If both `shmem_phys_lo` and `shmem_phys_hi` parameters are not
: all-ones bitwise then `shmem_phys_lo` specifies the lower XLEN
: bits and `shmem_phys_hi` specifies the upper XLEN bits of the
: shared memory physical base address. The `shmem_phys_lo` MUST
: be `(XLEN / 8)` byte aligned and the size of shared memory is
: assumed to be `trig_max * (XLEN / 2)` bytes.

For more details see the current version of the proposal:
- https://lists.riscv.org/g/tech-debug/message/1302

On the other hand, on RV32, the M-mode can only access the first 4GB of
the physical address space because M-mode does not have MMU to access
full 34-bit physical address space. Similarly, on RV64, the M-mode can
only access memory addressed by 64 bits.

This commit checks shmem address in function sbi_dbtr_setup_shmem
to make sure that shmem_phys_hi part of the valid address is zero.
Besides, the macro DBTR_SHMEM_MAKE_PHYS is updated to take into
account only low XLEN part.

Signed-off-by: Sergey Matyukevich &lt;geomatsi@gmail.com&gt;
Reviewed-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>docs: Fix wrong filename</title>
<updated>2024-06-28T03:04:15+00:00</updated>
<author>
<name>Jacob Lin</name>
<email>lovetaeyeon507@gmail.com</email>
</author>
<published>2024-06-27T03:21:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=0e45b634713d8a67d8a905e8970e93682c1db64f'/>
<id>urn:sha1:0e45b634713d8a67d8a905e8970e93682c1db64f</id>
<content type='text'>
Correct the compiled FW_PAYLOAD firmware ELF filename.

Signed-off-by: Jacob Lin &lt;lovetaeyeon507@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: fwft: return SBI_EINVAL rather than SBI_ERR_INVALID_PARAM</title>
<updated>2024-06-26T12:44:49+00:00</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-06-24T10:29:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=caae2f7d455c78c509782e1eb8d47dfdd874b903'/>
<id>urn:sha1:caae2f7d455c78c509782e1eb8d47dfdd874b903</id>
<content type='text'>
Error code returned by the ecall handles should use the defines from
sbi_ecall_interface.h rather than sbi_error.h.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: fwft: check feature value to be exactly 1 or 0</title>
<updated>2024-06-26T12:43:54+00:00</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-06-24T10:29:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=e8717d126401435896b0e96c18e187f0b2431d5e'/>
<id>urn:sha1:e8717d126401435896b0e96c18e187f0b2431d5e</id>
<content type='text'>
As stated by the spec and pointed out by Andrew Jones, the value passed
for MISALIGNED_EXC_DELEG and PTE_AD_HW_UPDATING should be either 0 or 1.
Add check for these values and return SBI_EINVAL if not.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
