<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git/docs, branch master</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=master</id>
<link rel='self' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/'/>
<updated>2026-05-18T12:50:50+00:00</updated>
<entry>
<title>lib: utils: fdt_domain: add root-regions-inheritance policy</title>
<updated>2026-05-18T12:50:50+00:00</updated>
<author>
<name>Yu-Chien Peter Lin</name>
<email>peter.lin@sifive.com</email>
</author>
<published>2026-05-16T07:29:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=f36acaeb80a490339923a5ec01ac3707741f6b90'/>
<id>urn:sha1:f36acaeb80a490339923a5ec01ac3707741f6b90</id>
<content type='text'>
Introduce root-regions-inheritance DT property to control
copying of root domain memregions. Support 'all' and 'm-only'
modes, always inheriting firmware and M-only regions; behavior
matches m-only policy when property is absent.

Signed-off-by: Yu-Chien Peter Lin &lt;peter.lin@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260516072906.1427203-1-peter.lin@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>docs: platform: update qemu_virt.md</title>
<updated>2026-05-11T04:56:36+00:00</updated>
<author>
<name>Zhang RunMin</name>
<email>runmin.zhang@ingenic.com</email>
</author>
<published>2026-03-19T12:56:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=3d8f1f386479219c4236b5c0fe483442c1bc7461'/>
<id>urn:sha1:3d8f1f386479219c4236b5c0fe483442c1bc7461</id>
<content type='text'>
When using GDB for debugging, if FW_TEXT_START is not set to 0x80000000
during compilation, the following error occurs:

Reading symbols from build/platform/generic/firmware/fw_payload.elf...
Remote debugging using localhost:1234
mips_warm_boot ()
    at /home/zrmin/opensbi/platform/generic/mips/mips_warm_boot.S:11
11      j       _start_warm
(gdb) b _start
Breakpoint 1 at 0x0: file /home/zrmin/opensbi/firmware/fw_base.S, line 50.
(gdb) c
Continuing.
Remote connection closed
(gdb)

With FW_TEXT_START=0x80000000, debugging works correctly:
Reading symbols from build/platform/generic/firmware/fw_payload.elf...
Remote debugging using localhost:1234
0x0000000000001000 in ?? ()
(gdb) b _start
Breakpoint 1 at 0x80000000: file /home/zrmin/opensbi/firmware/fw_base.S, line 50.
(gdb) c
Continuing.

Breakpoint 1, _start () at /home/zrmin/opensbi/firmware/fw_base.S:50
50      MOV_3R  s0, a0, s1, a1, s2, a2
(gdb)

This is because QEMU loads OpenSBI at address 0x80000000. When
FW_TEXT_START does not match this address, the debug symbols are
incorrectly offset, causing GDB to fail to set breakpoints properly.

Signed-off-by: Zhang RunMin &lt;runmin.zhang@ingenic.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260319125641.480161-1-runmin.zhang@ingenic.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fdt_domain: Default boot-hart to coldboot HART for multi-domain boot</title>
<updated>2026-05-11T04:41:06+00:00</updated>
<author>
<name>Yu-Chien Peter Lin</name>
<email>peter.lin@sifive.com</email>
</author>
<published>2026-03-27T05:49:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=8cd279e321ce8eedd2750d3e2ed9a906e43e6e38'/>
<id>urn:sha1:8cd279e321ce8eedd2750d3e2ed9a906e43e6e38</id>
<content type='text'>
When "boot-hart" is not specified, dom-&gt;boot_hartid was left as -1U,
causing domain context switching to fail. Default it to the coldboot
HART to enable SMP boot in multi-domain setups, consistent with how
next-arg1 is handled.

Also update its description in domain_support.md.

Signed-off-by: Yu-Chien Peter Lin &lt;peter.lin@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260327054936.3462935-1-peter.lin@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Tenstorrent Atlantis support</title>
<updated>2026-05-09T15:27:50+00:00</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2026-04-24T06:25:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=6767861c484d07f180f3dd710b5dc59f0c525374'/>
<id>urn:sha1:6767861c484d07f180f3dd710b5dc59f0c525374</id>
<content type='text'>
Add the Tenstorrent Atlantis as a generic-platform. This initial support
enables the single_fw_region option, and verifies and prints HART PMA
CSR configuration.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Remove kendryte/k210 platform</title>
<updated>2026-05-09T07:35:51+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-09T04:53:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=f34cf05347325515527ea9fdb658cf8063354aea'/>
<id>urn:sha1:f34cf05347325515527ea9fdb658cf8063354aea</id>
<content type='text'>
The kendryte/k210 platform does not have MMU support in S-mode hence
only NOMMU kernel which runs in M-mode can be used on this platform.

As of now, there is no clear use-case of supporting OpenSBI for
kendryte/k210 platform.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260409045310.2045739-1-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: ariane: Move ariane platform from fpga to generic</title>
<updated>2025-11-05T15:52:41+00:00</updated>
<author>
<name>Manuel Hernández Méndez</name>
<email>maherme.dev@gmail.com</email>
</author>
<published>2025-10-23T09:03:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=e8dfa55f3d6ada2e1f71671213bd3a68ec96ea76'/>
<id>urn:sha1:e8dfa55f3d6ada2e1f71671213bd3a68ec96ea76</id>
<content type='text'>
The Ariane framework has a generic PMU that is not used by OpenSBI.
Due to OpenSBI’s build system we cannot directly reuse the generic
platform functions, so move the Ariane platform to generic. Also due
to the generic platform is where new features are added.

Signed-off-by: Manuel Hernández Méndez &lt;maherme.dev@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: openpiton: Move openpiton platform from fpga to generic</title>
<updated>2025-08-26T11:38:00+00:00</updated>
<author>
<name>Manuel Hernández Méndez</name>
<email>maherme.dev@gmail.com</email>
</author>
<published>2025-08-13T10:47:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=525ac970b3c2b1549c8747959cfc4f9b84e1f711'/>
<id>urn:sha1:525ac970b3c2b1549c8747959cfc4f9b84e1f711</id>
<content type='text'>
The OpenPiton framework has a generic PMU that is not used by OpenSBI.
Due to OpenSBI’s build system we cannot directly reuse the generic
platform functions, so move the OpenPiton platform to generic. Also due
to the generic platform is where new features are added.

Signed-off-by: Manuel Hernández Méndez &lt;maherme.dev@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250813104759.33276-1-maherme.dev@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>docs: pmu_support: fix example typos</title>
<updated>2025-04-14T11:55:54+00:00</updated>
<author>
<name>Leo Yu-Chi Liang</name>
<email>ycliang@andestech.com</email>
</author>
<published>2025-03-24T04:39:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=5ab908d6227e6021678cca57d7040d9401a3615e'/>
<id>urn:sha1:5ab908d6227e6021678cca57d7040d9401a3615e</id>
<content type='text'>
The (event ID &amp; "second column mask") should equal
the "first column match value". Modify the example
to fit the description.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Link: https://lore.kernel.org/r/20250324043943.2513070-1-ycliang@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: Emit lr and sc instructions based on -march flags</title>
<updated>2025-03-28T13:22:05+00:00</updated>
<author>
<name>Chao-ying Fu</name>
<email>icebergfu@gmail.com</email>
</author>
<published>2025-02-26T01:47:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=995f226f3f335864d2fca6254af32fa7ab0162e6'/>
<id>urn:sha1:995f226f3f335864d2fca6254af32fa7ab0162e6</id>
<content type='text'>
When -march=rv64im_zalrsc_zicsr is used, provide atomic operations
and locks using lr and sc instructions only.

Signed-off-by: Chao-ying Fu &lt;cfu@mips.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: introduce DT-based configurable heap size</title>
<updated>2024-11-11T12:18:45+00:00</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@gmail.com</email>
</author>
<published>2024-11-11T02:27:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=5d4e3fb2ee03b9894d9cb03ddac0cda83d7ccc71'/>
<id>urn:sha1:5d4e3fb2ee03b9894d9cb03ddac0cda83d7ccc71</id>
<content type='text'>
The default heap size will work for most platforms, but for some
special platforms, the heap is too small to hold all the information
or is too big so that it take too much ram. Introduce configurable
heap should solve this problem and make all generic platforms happy.

Add DT-based heap-size for the generic platform.

Signed-off-by: Inochi Amaoto &lt;inochiama@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
