<feed xmlns='http://www.w3.org/2005/Atom'>
<title>software/src/opensbi.git/lib/sbi/sbi_unpriv.c, branch master</title>
<subtitle>RISC-V Open Source Supervisor Binary Interface</subtitle>
<id>https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/atom?h=master</id>
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<updated>2026-06-17T06:11:11+00:00</updated>
<entry>
<title>lib: sbi: Add variable-length unprivilege access functions</title>
<updated>2026-06-17T06:11:11+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2026-06-09T06:00:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=914aeddaf16d91d39112056c5dd2b013b757a424'/>
<id>urn:sha1:914aeddaf16d91d39112056c5dd2b013b757a424</id>
<content type='text'>
sbi_load/store_loop read/write variable-length buffer unprivileged.
Both function use the widest aligned 8/4/2/1 byte load/stores in each
loop to reduce the total number of iterations.

Also switch the scalar/vector misaligned handlers to make use of such
functions to simplify code.

Miscellaneous: remove the unnecessary [taddr] in inline assembly

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Tested-by: Anirudh Srinivasan &lt;asrinivasan@oss.tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260609060024.706-4-ganboing@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()</title>
<updated>2025-07-20T15:24:34+00:00</updated>
<author>
<name>Alvin Chang</name>
<email>alvinga@andestech.com</email>
</author>
<published>2025-07-03T15:19:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=ea5abd1f5e33ed3afedc92686ec8bfd00bc49235'/>
<id>urn:sha1:ea5abd1f5e33ed3afedc92686ec8bfd00bc49235</id>
<content type='text'>
The variable "sbi_hart_expected_trap" has already been extern variable.
Therefore, the program can directly refer to it instead of calling
sbi_hart_expected_trap_addr().

Signed-off-by: Alvin Chang &lt;alvinga@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250703151957.2545958-2-alvinga@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Remove unnecessary semicolon</title>
<updated>2023-05-11T07:01:34+00:00</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-04-25T08:56:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=4e3353057a3b975ca58c9b831749e2760f7812c0'/>
<id>urn:sha1:4e3353057a3b975ca58c9b831749e2760f7812c0</id>
<content type='text'>
We have redundant semicolon at quite a few places so let's remove it.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Fix tval and tinst for sbi_get_insn()</title>
<updated>2022-06-21T03:01:56+00:00</updated>
<author>
<name>dramforever</name>
<email>dramforever@live.com</email>
</author>
<published>2022-06-09T07:07:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=a07402ac9cea19b3af70ed6469bb6d937132a18f'/>
<id>urn:sha1:a07402ac9cea19b3af70ed6469bb6d937132a18f</id>
<content type='text'>
We should not change trap-&gt;tval to mepc because mtval already points to
the faulting portion of the emulated instruction fetch, which is also
what stval is expected to be.

In addition, htinst is only allowed to be zero for instruction access
faults or page faults, and is only allowed to be zero or a
psuedoinstruction for instruction guest-page faults. Fix trap-&gt;tinst for
these cases.

Signed-off-by: dramforever &lt;dramforever@live.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: Add error messages via conditional compilation for the future</title>
<updated>2022-03-27T03:24:12+00:00</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2022-03-15T16:22:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=d552fc8d369780150fd9837e1097b4b34a640d12'/>
<id>urn:sha1:d552fc8d369780150fd9837e1097b4b34a640d12</id>
<content type='text'>
On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved.
Through this conditional compile, the corresponding implementation
can be prompted to be added.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: Optimize inline assembly for unprivilege access functions</title>
<updated>2020-05-16T12:22:42+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-05-15T22:30:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=36833abfbb48ddf6a959b09c9e0e341ae33a811a'/>
<id>urn:sha1:36833abfbb48ddf6a959b09c9e0e341ae33a811a</id>
<content type='text'>
Currently, unprivileged access functions uses few additional instructions
which are redundant. It also uses specific registers which are not necessary.

Remove those additional instructions and let the compiler choose the
registers.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Rename unprivileged trap handler</title>
<updated>2020-05-10T04:29:16+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-05-09T23:47:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=63a513edeccee1758bbfe5111ccc4fbec8f18a12'/>
<id>urn:sha1:63a513edeccee1758bbfe5111ccc4fbec8f18a12</id>
<content type='text'>
Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.

Rename it to "expected" trap handler as it will be used in other cases in
future.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Tested-by: Jonathan Balkind &lt;jbalkind@cs.princeton.edu&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Remove scratch parameter from unpriv load/store functions</title>
<updated>2020-03-28T08:02:01+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-19T12:07:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=626467cfd96f99230ff5d83f98562f23aee291c3'/>
<id>urn:sha1:626467cfd96f99230ff5d83f98562f23aee291c3</id>
<content type='text'>
The scratch parameter of unpriv load/store functions is now redundant
hence we remove it.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Optimize unpriv load/store implementation</title>
<updated>2020-03-28T08:01:53+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-19T11:43:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=1de66d170e71fb94732ffc80dcf4e70e623c4f7a'/>
<id>urn:sha1:1de66d170e71fb94732ffc80dcf4e70e623c4f7a</id>
<content type='text'>
This patch optimize unpriv load/store implementation by having
dedicated unpriv trap handler (just like KVM RISC-V).

As a result of this optimization:
1. We have reduced roughly 13+ instruction in all unpriv load/store
   functions. The reduced instruction also include two function calls.
2. Per-HART trap info pointer in scratch space is now redundant
   hence removed.
3. The sbi_trap_handler() is now much cleaner because we don't have
   to handle unpriv load/store traps.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: Move bits related defines and macros to sbi_bitops.h</title>
<updated>2020-03-08T05:36:18+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-04T05:38:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.rulkc.org/pub/scm/riscv/software/src/opensbi.git/commit/?id=00d332bbe726d85e4c2b81ab0a08182612f96c03'/>
<id>urn:sha1:00d332bbe726d85e4c2b81ab0a08182612f96c03</id>
<content type='text'>
The right location for all bits related defines and macros is
sbi_bitops.h hence this patch. With this patch, the sbi_bits.h
is redundant so we remove it.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
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