software/src/opensbi.git/platform/generic/configs/defconfig, branch master

lib: utils/mpxy: Add RPMI MPXY driver for logging service group

2026-07-01T16:00:24+00:00

Add RPMI MPXY proxy driver for LOGGING service group so that S-mode can leverage LOGGING service group implemented by the platform microcontroller. Reviewed-by: Rahul Pathak Signed-off-by: Subrahmanya Lingappa Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/reset: Add litex SoC reset driver

2026-06-15T04:40:25+00:00

Litex SoC controller supports reboot function by toggling the first bit of the ctrl register. Add a reset driver so other software can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260529085234.1682842-1-inochiama@gmail.com Signed-off-by: Anup Patel

lib: utils/reset: add SpacemiT P1 PMIC support

2026-05-11T13:51:31+00:00

The SpacemiT P1 is a PMIC commonly found with SpacemiT CPU like K1. Add a reset driver for it. Signed-off-by: Aurelien Jarno Tested-by: Anand Moon Link: https://lore.kernel.org/r/20260419150857.2705843-3-aurelien@aurel32.net Signed-off-by: Anup Patel

lib: utils/i2c: add minimal SpacemiT I2C driver

2026-05-11T13:51:31+00:00

Add a simple SpacemiT I2C driver for basic byte transfers over the I2C bus, prioritizing simplicity over performance. The driver operates in PIO mode and does not use interrupts, FIFO, or DMA. The controller is reset at the start of each transaction to ensure a known initial state, regardless of prior configuration by the kernel. This also avoids the need for additional error recovery code. This will be used for communication with onboard PMIC to reset and power-off the board. Signed-off-by: Aurelien Jarno Tested-by: Anand Moon Link: https://lore.kernel.org/r/20260419150857.2705843-2-aurelien@aurel32.net Signed-off-by: Anup Patel

platform: generic: Tenstorrent Atlantis support

2026-05-09T15:27:50+00:00

Add the Tenstorrent Atlantis as a generic-platform. This initial support enables the single_fw_region option, and verifies and prints HART PMA CSR configuration. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com Signed-off-by: Anup Patel

lib: utils: Add MPXY client driver for RPMI MM service group

2026-04-06T12:53:25+00:00

Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L Signed-off-by: Ranbir Singh Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel

platform: sifive: Add initial support for SiFive development platform

2026-04-06T05:19:21+00:00

Add initial platform support for SiFive development platforms with the "sifive-dev" compatible string. Reviewed-by: Greentime Hu Reviewed-by: Zong Li Signed-off-by: Yu-Chien Peter Lin Link: https://lore.kernel.org/r/20260224031733.3817148-1-peter.lin@sifive.com Signed-off-by: Anup Patel

platform: generic: mips: add P8700 based "eyeq7h" and "boston"

2026-02-25T13:19:03+00:00

Refactor MIPS P8700 support, convert P8700 into a "CPU" and add 2 platforms using this CPU: - "boston" - FPGA platform developed by MIPS - "eyeq7h" - automotive platform by Mobileye Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

lib: utils/serial: Add support for Altera JTAG UART

2026-02-20T11:20:35+00:00

Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel

lib: utils/suspend: add Andes ATCSMU suspend driver

2026-02-11T06:44:04+00:00

Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel