software/src/opensbi.git/platform, branch master

lib: utils/mpxy: Add RPMI MPXY driver for logging service group

2026-07-01T16:00:24+00:00

Add RPMI MPXY proxy driver for LOGGING service group so that S-mode can leverage LOGGING service group implemented by the platform microcontroller. Reviewed-by: Rahul Pathak Signed-off-by: Subrahmanya Lingappa Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com Signed-off-by: Anup Patel

platform: generic: spacemit: k1: fix wrong address definitions

2026-06-28T05:46:36+00:00

PMU_AP_CORE2_IDLE_CFG and PMU_AP_CORE3_IDLE_CFG are not continuous with PMU_AP_CORE0_IDLE_CFG and PMU_AP_CORE1_IDLE_CFG. They are at PMU AP base + 0x160 and + 0x164, matching the vendor OpenSBI definitions. After fixing these addresses, the intermediate cluster offset macros are redundant now, so define the wakeup and idle registers directly as PMU_AP_BASE offsets. This makes the actual register addresses easier to inspect and compare against the vendor code. C1_RVBADDR_HI_ADDR is also corrected according to the vendor OpenSBI definition. This was tested by writing an invalid value to the corrected address, which prevents cluster1 CPUs from coming online, while doing the same with the old address does not affect SMP boot. Fixes: 1f84ec2a ("platform: generic: spacemit: add K1") Signed-off-by: Junhui Liu Link: https://lore.kernel.org/r/20260623-k1-fix-addr-v1-1-3dbde8c03bd6@pigmoral.tech Signed-off-by: Anup Patel

platform: generic: mips eyeq7h: fix boot with JTAG

2026-06-28T05:38:13+00:00

When JTAG is connected, internal logic leads to the bit MIPS_CTL0_DBG_RST_DASRT (for the debug unit) stay high and this prevents normal cluster power-up. Force proper power-on reset value prior to power-up sequence. Hold this value for about 10 usec Signed-off-by: Vladimir Kondratiev Link: https://lore.kernel.org/r/20260618103713.2588984-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel

platform: generic: eswin: Add eic770x_hsm and fix warm reset issues

2026-06-15T05:08:09+00:00

During warm reset, my EIC770X/Hifive Premier P550 can sometimes encounter memory corruption issue crashing Linux boot. Currently the issue is mitigated by having a sbi_printf before writing to the reset register. I analyzed the issue further since then. From the SoC datasheet[1], it's recommended to implement power-down flow as: a. Designate a primary core, and let it broadcast requests to other cores to execute a CEASE insn. Primary core also notifies an "Externel Agent" to start monitoring. b. Primary core waits for other cores to CEASE before it CEASEs. c. "External Agent" waits for primary core to CEASE before resets the Core Complex. It's possible that EIC770X can trigger undefined behavior if the core complex is reset while the harts are actively running. The sbi_printf in the reset handler effectively hides the problem by delaying the reset -- by the time sbi_printf finishes, all other harts will have already landed in the loop in sbi_hsm_hart_wait(), which parks the hart. Without the sbi_printf, I confirmed that other harts haven't reached sbi_hsm_hart_wait yet before current hart resets the SoC. (by debugging) To safely reset, and inspired by the datasheet, the warm reset logic in eic770x.c now use the current hart as both primary core and the "External Agent", and other harts as secondary cores. It leverages the HSM framework and a new eic770x_hsm device to CEASE other harts, and wait for them to CEASE before resets the SoC. with the sbi_printf before reset removed, and this logic in place, stress test shows that the memory corruption issue no longer occurs. The new eic770x_hsm device is only used for the reset-CEASE logic at the moment, and may be extended to a fully functional HSM device in the future. [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual Fixes: e5797e0688c1 ("platform: generic: eswin: add EIC7700") Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260605075708.96-3-ganboing@gmail.com Signed-off-by: Anup Patel

lib: utils/reset: Add litex SoC reset driver

2026-06-15T04:40:25+00:00

Litex SoC controller supports reboot function by toggling the first bit of the ctrl register. Add a reset driver so other software can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260529085234.1682842-1-inochiama@gmail.com Signed-off-by: Anup Patel

platform: generic: Optimize extensions_init() to parse ISA extensions once

2026-06-12T10:38:29+00:00

Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

platform: Fix payload alignment when FW_TEXT_START isn't 2M/4M aligned

2026-06-12T03:25:39+00:00

The payload for FW_PAYLOAD needs to be placed at a 2M/4M aligned address (for 64/32 bit systems) and the current makefile uses FW_PAYLOAD_OFFSET to achieve this. This only works if FW_TEXT_START is already 2M/4M aligned. Most existing physical/virtual platforms have used a FW_TEXT_START of 0x0 or 0x80000000, so this hasn't been an issue so far. If, for example, FW_TEXT_START is 0x80000, the payload would end up placed at 0x280000 on a 64 bit system, which isn't a 2M aligned address. Update the makefile to use FW_PAYLOAD_ALIGN instead. This will ensure that the address picked for the payload is 2M/4M aligned irrespective of where FW_TEXT_START is. Signed-off-by: Anirudh Srinivasan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260508-payload_alignment-v1-1-6628b4ec1ed3@oss.tenstorrent.com Signed-off-by: Anup Patel

lib: sbi: Add hart_ prefix to PMP functions

2026-06-10T12:07:49+00:00

PMP functions that deal with hart PMP CSRs are given a sbi_hart_ prefix, to distinguish from RISC-V PMP encoding functions. The is_pmp_entry_mapped() function is changed a little more, to align with other PMP conventions, and made to return a bool to make it more obvious that it returns a bool and not an SBI_ return code. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260430045528.420437-8-npiggin@gmail.com Signed-off-by: Anup Patel

lib: utils/reset: add SpacemiT P1 PMIC support

2026-05-11T13:51:31+00:00

The SpacemiT P1 is a PMIC commonly found with SpacemiT CPU like K1. Add a reset driver for it. Signed-off-by: Aurelien Jarno Tested-by: Anand Moon Link: https://lore.kernel.org/r/20260419150857.2705843-3-aurelien@aurel32.net Signed-off-by: Anup Patel

lib: utils/i2c: add minimal SpacemiT I2C driver

2026-05-11T13:51:31+00:00

Add a simple SpacemiT I2C driver for basic byte transfers over the I2C bus, prioritizing simplicity over performance. The driver operates in PIO mode and does not use interrupts, FIFO, or DMA. The controller is reset at the start of each transaction to ensure a known initial state, regardless of prior configuration by the kernel. This also avoids the need for additional error recovery code. This will be used for communication with onboard PMIC to reset and power-off the board. Signed-off-by: Aurelien Jarno Tested-by: Anand Moon Link: https://lore.kernel.org/r/20260419150857.2705843-2-aurelien@aurel32.net Signed-off-by: Anup Patel