Merge changes I4c66f31c,Iab216270,I60f76ff0,I859a1183,I19f42c68, ... into integration

* changes:
  fix(st): cast clk_get_rate return when setting console
  fix(st): cast the read_cntfrq_el0() return to unsigned int
  fix(st-clock): correct some STM32MP15 clock driver function
  fix(st-pmic): store regulator ID as an uint8_t
  fix(st-regulator): remove const for driver_data
  fix(st-pmic): stub some functions for STPMIC1L
  fix(st-sdmmc2): update plat_sdmmc2_use_dma prototype
  fix(st-drivers): use BIT_32/GENMASK_32 in ST drivers

15 files changed, 74 insertions, 82 deletions

diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index 67370278f..a6b2717f8 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c
@@ -42,7 +42,7 @@ static uint32_t otp_bank(uint32_t otp)
 
 static uint32_t otp_bit_mask(uint32_t otp)
 {
-	return BIT(otp & BSEC_OTP_MASK);
+	return BIT_32(otp & BSEC_OTP_MASK);
 }
 
 /*
diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c
index a4bddbf4d..a5e6b1de6 100644
--- a/drivers/st/clk/clk-stm32-core.c
+++ b/drivers/st/clk/clk-stm32-core.c
@@ -71,7 +71,7 @@ static int clk_gate_enable(struct stm32_clk_priv *priv, int id)
 	const struct clk_stm32 *clk = _clk_get(priv, id);
 	struct clk_gate_cfg *cfg = clk->clock_cfg;
 
-	mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx));
+	mmio_setbits_32(priv->base + cfg->offset, BIT_32(cfg->bit_idx));
 
 	/* Make sure the clock register has been written */
 	(void)mmio_read_32(priv->base + cfg->offset);
@@ -86,7 +86,7 @@ static void clk_gate_disable(struct stm32_clk_priv *priv, int id)
 
 	dmbsy(); /* Ensure previous transactions are performed. */
 
-	mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx));
+	mmio_clrbits_32(priv->base + cfg->offset, BIT_32(cfg->bit_idx));
 
 	/* Make sure the clock register has been written */
 	(void)mmio_read_32(priv->base + cfg->offset);
@@ -97,7 +97,7 @@ static bool clk_gate_is_enabled(struct stm32_clk_priv *priv, int id)
 	const struct clk_stm32 *clk = _clk_get(priv, id);
 	struct clk_gate_cfg *cfg = clk->clock_cfg;
 
-	return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U);
+	return ((mmio_read_32(priv->base + cfg->offset) & BIT_32(cfg->bit_idx)) != 0U);
 }
 
 const struct stm32_clk_ops clk_gate_ops = {
@@ -112,9 +112,9 @@ void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id)
 	uintptr_t addr = priv->base + gate->offset;
 
 	if (gate->set_clr != 0U) {
-		mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx));
+		mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT_32(gate->bit_idx));
 	} else {
-		mmio_clrbits_32(addr, BIT(gate->bit_idx));
+		mmio_clrbits_32(addr, BIT_32(gate->bit_idx));
 	}
 }
 
@@ -124,10 +124,10 @@ int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id)
 	uintptr_t addr = priv->base + gate->offset;
 
 	if (gate->set_clr != 0U) {
-		mmio_write_32(addr, BIT(gate->bit_idx));
+		mmio_write_32(addr, BIT_32(gate->bit_idx));
 
 	} else {
-		mmio_setbits_32(addr, BIT(gate->bit_idx));
+		mmio_setbits_32(addr, BIT_32(gate->bit_idx));
 	}
 
 	return 0;
@@ -151,7 +151,7 @@ static const struct stm32_clk_ops *_clk_get_ops(struct stm32_clk_priv *priv, int
 	return priv->ops_array[clk->ops];
 }
 
-#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U)
+#define clk_div_mask(_width) GENMASK_32(((_width) - 1U), 0U)
 
 static unsigned int _get_table_div(const struct clk_div_table *table,
 				   unsigned int val)
@@ -176,11 +176,11 @@ static unsigned int _get_div(const struct clk_div_table *table,
 	}
 
 	if ((flags & CLK_DIVIDER_POWER_OF_TWO) != 0UL) {
-		return BIT(val);
+		return BIT_32(val);
 	}
 
 	if ((flags & CLK_DIVIDER_MAX_AT_ZERO) != 0UL) {
-		return (val != 0U) ? val : BIT(width);
+		return (val != 0U) ? val : BIT_32(width);
 	}
 
 	if (table != NULL) {
@@ -208,7 +208,7 @@ int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)
 
 	timeout = timeout_init_us(CLKSRC_TIMEOUT);
 
-	mask = BIT(mux->bitrdy);
+	mask = BIT_32(mux->bitrdy);
 
 	while ((mmio_read_32(address) & mask) == 0U) {
 		if (timeout_elapsed(timeout)) {
@@ -708,7 +708,7 @@ int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t val
 	}
 
 	timeout = timeout_init_us(CLKSRC_TIMEOUT);
-	mask = BIT(divider->bitrdy);
+	mask = BIT_32(divider->bitrdy);
 
 	while ((mmio_read_32(address) & mask) == 0U) {
 		if (timeout_elapsed(timeout)) {
@@ -724,12 +724,12 @@ int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id,
 {
 	const struct gate_cfg *gate = &priv->gates[gate_id];
 	uintptr_t address = priv->base + gate->offset;
-	uint32_t mask_rdy = BIT(gate->bit_idx);
+	uint32_t mask_rdy = BIT_32(gate->bit_idx);
 	uint64_t timeout;
 	uint32_t mask_test;
 
 	if (ready_on) {
-		mask_test = BIT(gate->bit_idx);
+		mask_test = BIT_32(gate->bit_idx);
 	} else {
 		mask_test = 0U;
 	}
@@ -757,10 +757,10 @@ int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int id)
 	uintptr_t addr = priv->base + gate->offset;
 
 	if (gate->set_clr != 0U) {
-		mmio_write_32(addr, BIT(gate->bit_idx));
+		mmio_write_32(addr, BIT_32(gate->bit_idx));
 
 	} else {
-		mmio_setbits_32(addr, BIT(gate->bit_idx));
+		mmio_setbits_32(addr, BIT_32(gate->bit_idx));
 	}
 
 	return 0;
@@ -774,21 +774,21 @@ void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int id)
 	uintptr_t addr = priv->base + gate->offset;
 
 	if (gate->set_clr != 0U) {
-		mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx));
+		mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT_32(gate->bit_idx));
 	} else {
-		mmio_clrbits_32(addr, BIT(gate->bit_idx));
+		mmio_clrbits_32(addr, BIT_32(gate->bit_idx));
 	}
 }
 
 bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id)
 {
 	const struct gate_cfg *gate;
-	uint32_t addr;
+	uintptr_t addr;
 
 	gate = &priv->gates[gate_id];
 	addr = priv->base + gate->offset;
 
-	return ((mmio_read_32(addr) & BIT(gate->bit_idx)) != 0U);
+	return ((mmio_read_32(addr) & BIT_32(gate->bit_idx)) != 0U);
 }
 
 bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int id)
@@ -826,8 +826,8 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
 	return (unsigned long)(rate / cfg->div);
 };
 
-#define APB_DIV_MASK	GENMASK(2, 0)
-#define TIM_PRE_MASK	BIT(0)
+#define APB_DIV_MASK	GENMASK_32(2, 0)
+#define TIM_PRE_MASK	BIT_32(0)
 
 static unsigned long timer_recalc_rate(struct stm32_clk_priv *priv,
 				       int id, unsigned long prate)
diff --git a/drivers/st/clk/clk-stm32-core.h b/drivers/st/clk/clk-stm32-core.h
index 93d4c37e4..0f8878594 100644
--- a/drivers/st/clk/clk-stm32-core.h
+++ b/drivers/st/clk/clk-stm32-core.h
@@ -139,7 +139,7 @@ struct clk_gate_cfg {
 #define DIV_NO_BIT_RDY			UINT8_MAX
 
 #define MASK_WIDTH_SHIFT(_width, _shift) \
-	GENMASK(((_width) + (_shift) - 1U), (_shift))
+	GENMASK_32(((_width) + (_shift) - 1U), (_shift))
 
 void clk_stm32_rcc_regs_lock(void);
 void clk_stm32_rcc_regs_unlock(void);
diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index f9460016d..f34739ae9 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c
@@ -727,11 +727,11 @@ static void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id,
 	address = priv->base + bypass_data->offset;
 
 	if (digbyp) {
-		mmio_setbits_32(address, BIT(bypass_data->bit_digbyp));
+		mmio_setbits_32(address, BIT_32(bypass_data->bit_digbyp));
 	}
 
 	if (bypass || digbyp) {
-		mmio_setbits_32(address, BIT(bypass_data->bit_byp));
+		mmio_setbits_32(address, BIT_32(bypass_data->bit_byp));
 	}
 }
 
@@ -750,7 +750,7 @@ static void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id,
 	address = priv->base + css_data->offset;
 
 	if (css) {
-		mmio_setbits_32(address, BIT(css_data->bit_css));
+		mmio_setbits_32(address, BIT_32(css_data->bit_css));
 	}
 }
 
@@ -770,7 +770,7 @@ static void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id,
 
 	address = priv->base + drive_data->offset;
 
-	mask = (BIT(drive_data->drv_width) - 1U) <<  drive_data->drv_shift;
+	mask = (BIT_32(drive_data->drv_width) - 1U) <<  drive_data->drv_shift;
 
 	/*
 	 * Warning: not recommended to switch directly from "high drive"
@@ -2137,10 +2137,10 @@ static int wait_predivsr(uint16_t channel)
 
 	if (channel < __WORD_BIT) {
 		previvsr = rcc_base + RCC_PREDIVSR1;
-		channel_bit = BIT(channel);
+		channel_bit = BIT_32(channel);
 	} else {
 		previvsr = rcc_base + RCC_PREDIVSR2;
-		channel_bit = BIT(channel - __WORD_BIT);
+		channel_bit = BIT_32(channel - __WORD_BIT);
 	}
 
 	timeout = timeout_init_us(CLKDIV_TIMEOUT);
@@ -2165,10 +2165,10 @@ static int wait_findivsr(uint16_t channel)
 
 	if (channel < __WORD_BIT) {
 		finvivsr = rcc_base + RCC_FINDIVSR1;
-		channel_bit = BIT(channel);
+		channel_bit = BIT_32(channel);
 	} else {
 		finvivsr = rcc_base + RCC_FINDIVSR2;
-		channel_bit = BIT(channel - __WORD_BIT);
+		channel_bit = BIT_32(channel - __WORD_BIT);
 	}
 
 	timeout = timeout_init_us(CLKDIV_TIMEOUT);
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 45bdc88ba..1c50d75da 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -211,22 +211,6 @@ static const struct mux_cfg parent_mp15[MUX_NB] = {
 #define MASK_WIDTH_SHIFT(_width, _shift) \
 	GENMASK(((_width) + (_shift) - 1U), (_shift))
 
-int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id)
-{
-	const struct mux_cfg *mux;
-	uint32_t mask;
-
-	if (mux_id >= priv->nb_parents) {
-		panic();
-	}
-
-	mux = &priv->parents[mux_id];
-
-	mask = MASK_WIDTH_SHIFT(mux->width, mux->shift);
-
-	return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift;
-}
-
 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)
 {
 	const struct mux_cfg *mux = &priv->parents[pid];
@@ -264,7 +248,7 @@ static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val)
 	return clk_mux_set_parent(priv, mux, sel);
 }
 
-int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value)
+static int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value)
 {
 	const struct div_cfg *divider;
 	uintptr_t address;
diff --git a/drivers/st/crypto/stm32_rng.c b/drivers/st/crypto/stm32_rng.c
index 9e5135869..c6e89a105 100644
--- a/drivers/st/crypto/stm32_rng.c
+++ b/drivers/st/crypto/stm32_rng.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2026, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -320,14 +320,14 @@ int stm32_rng_init(void)
 
 		if (dt_rng.reset >= 0) {
 
-			ret = stm32mp_reset_assert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS);
+			ret = stm32mp_reset_assert((uint32_t)dt_rng.reset, TIMEOUT_US_1MS);
 			if (ret != 0) {
 				panic();
 			}
 
 			udelay(20);
 
-			ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS);
+			ret = stm32mp_reset_deassert((uint32_t)dt_rng.reset, TIMEOUT_US_1MS);
 			if (ret != 0) {
 				panic();
 			}
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 01c4c878c..faa0d50c5 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2026, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -310,9 +310,9 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 	clk_enable(clock);
 
 	if (secure) {
-		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
+		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT_32(pin));
 	} else {
-		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
+		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT_32(pin));
 	}
 
 	clk_disable(clock);
@@ -336,9 +336,9 @@ void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level)
 	clk_enable(clock);
 
 	if (level == GPIO_LEVEL_HIGH) {
-		mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin));
+		mmio_write_32(base + GPIO_BSRR_OFFSET, BIT_32(pin));
 	} else {
-		mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U));
+		mmio_write_32(base + GPIO_BSRR_OFFSET, BIT_32(pin + 16U));
 	}
 
 	VERBOSE("GPIO %u level set to 0x%x\n", bank,
@@ -357,7 +357,7 @@ enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin)
 
 	clk_enable(clock);
 
-	if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) {
+	if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT_32(pin)) {
 		level = GPIO_LEVEL_HIGH;
 	}
 
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 6bbcc987b..d3db6ce13 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -163,7 +163,7 @@ static struct stm32_sdmmc2_params sdmmc2_params;
 static bool next_cmd_is_acmd;
 
 #pragma weak plat_sdmmc2_use_dma
-bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
+bool plat_sdmmc2_use_dma(uintptr_t instance, uintptr_t memory)
 {
 	return false;
 }
diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c
index 27488ee88..5f6f9070d 100644
--- a/drivers/st/pmic/stm32mp_pmic2.c
+++ b/drivers/st/pmic/stm32mp_pmic2.c
@@ -23,7 +23,7 @@
 #define PMIC_NODE_NOT_FOUND	1
 
 struct regul_handle_s {
-	const uint32_t id;
+	const uint8_t id;
 	uint16_t bypass_mv;
 };
 
@@ -198,11 +198,6 @@ void pmic_switch_off(void)
 	panic();
 }
 
-int pmic_voltages_init(void)
-{
-	return 0;
-}
-
 static int pmic2_set_state(const struct regul_description *desc, bool enable)
 {
 	struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
@@ -310,26 +305,25 @@ static int pmic2_list_voltages(const struct regul_description *desc,
 static int pmic2_set_flag(const struct regul_description *desc, uint16_t flag)
 {
 	struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
-	uint32_t id = regul->id;
 	int ret = -EPERM;
 
 	VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag);
 
 	switch (flag) {
 	case REGUL_PULL_DOWN:
-		ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_PULL_DOWN, 1U);
+		ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_PULL_DOWN, 1U);
 		break;
 	case REGUL_OCP:
-		ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_OCP, 1U);
+		ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_OCP, 1U);
 		break;
 	case REGUL_SINK_SOURCE:
-		ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_SINK_SOURCE, 1U);
+		ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_SINK_SOURCE, 1U);
 		break;
 	case REGUL_ENABLE_BYPASS:
-		ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_BYPASS, 1U);
+		ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_BYPASS, 1U);
 		break;
 	case REGUL_MASK_RESET:
-		ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_MASK_RESET, 1U);
+		ret = stpmic2_regulator_set_prop(pmic2, regul->id, STPMIC2_MASK_RESET, 1U);
 		break;
 	default:
 		ERROR("Invalid flag %u", flag);
diff --git a/drivers/st/reset/stm32mp2_reset.c b/drivers/st/reset/stm32mp2_reset.c
index 0918df59e..d8619aa6b 100644
--- a/drivers/st/reset/stm32mp2_reset.c
+++ b/drivers/st/reset/stm32mp2_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2026, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,7 +28,7 @@ static uint8_t id2reg_bit_pos(unsigned int reset_id)
 static int reset_toggle(uint32_t id, unsigned int to_us, bool reset_status)
 {
 	uint32_t offset = id2reg_offset(id);
-	uint32_t bitmsk = BIT(id2reg_bit_pos(id));
+	uint32_t bitmsk = BIT_32(id2reg_bit_pos(id));
 	uint32_t bit_check;
 	uintptr_t rcc_base = stm32mp_rcc_base();
 
diff --git a/drivers/st/rif/stm32_rifsc.c b/drivers/st/rif/stm32_rifsc.c
index f025c31bd..977781745 100644
--- a/drivers/st/rif/stm32_rifsc.c
+++ b/drivers/st/rif/stm32_rifsc.c
@@ -29,7 +29,7 @@ void stm32_rifsc_ip_configure(int rimu_id, int rifsc_id, uint32_t param)
 	assert(rifsc_id < STM32MP25_RIFSC_MAX_ID);
 #endif /* STM32MP25 */
 
-	bit = BIT(rifsc_id % U(32));
+	bit = BIT_32(rifsc_id % U(32));
 
 	/* Set peripheral accesses to Secure/Privilege only */
 	mmio_setbits_32(RIFSC_BASE + _RIFSC_RISC_SECCFGR(rifsc_id), bit);
diff --git a/include/drivers/st/regulator.h b/include/drivers/st/regulator.h
index bf583e224..d07f84912 100644
--- a/include/drivers/st/regulator.h
+++ b/include/drivers/st/regulator.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2026, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,7 +68,7 @@ int regulator_set_flag(struct rdev *rdev, uint16_t flag);
 struct regul_description {
 	const char *node_name;
 	const struct regul_ops *ops;
-	const void *driver_data;
+	void *driver_data;
 	const char *supply_name;
 	const uint32_t enable_ramp_delay;
 };
diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h
index c83f62509..9f5e7af66 100644
--- a/include/drivers/st/stm32_sdmmc2.h
+++ b/include/drivers/st/stm32_sdmmc2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2026, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,6 +30,6 @@ struct stm32_sdmmc2_params {
 
 unsigned long long stm32_sdmmc2_mmc_get_device_size(void);
 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params);
-bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory);
+bool plat_sdmmc2_use_dma(uintptr_t instance, uintptr_t memory);
 
 #endif /* STM32_SDMMC2_H */
diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h
index ba25a6ed1..cd185497d 100644
--- a/include/drivers/st/stm32mp_pmic.h
+++ b/include/drivers/st/stm32mp_pmic.h
@@ -33,7 +33,7 @@ bool initialize_pmic_i2c(void);
  */
 void initialize_pmic(void);
 
-#if DEBUG
+#if DEBUG && !STM32MP_STPMIC1L
 void print_pmic_info_and_debug(void);
 #else
 static inline void print_pmic_info_and_debug(void)
@@ -46,7 +46,14 @@ static inline void print_pmic_info_and_debug(void)
  *
  * Returns 0 on success, and negative values on errors
  */
+#if STM32MP_STPMIC1L
+static inline int pmic_voltages_init(void)
+{
+	return 0;
+}
+#else
 int pmic_voltages_init(void);
+#endif
 
 /*
  * pmic_switch_off - switch off the platform with PMIC
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 3c7129b70..b6f076cb3 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2026, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -70,7 +70,14 @@ uintptr_t plat_get_ns_image_entrypoint(void)
 
 unsigned int plat_get_syscnt_freq2(void)
 {
-	return read_cntfrq_el0();
+	/*
+	 * The system counter clock will never be above 4GHz, it is usually set
+	 * at 64MHz (HSI) at startup, and then moved to another clock with a
+	 * lower frequency and more stable.
+	 * It is then safe to cast the return of read_cntfrq_el0 to a 32 bit
+	 * value to match the plat_get_syscnt_freq2 function prototype.
+	 */
+	return (unsigned int)read_cntfrq_el0();
 }
 
 static uintptr_t boot_ctx_address;
@@ -293,7 +300,7 @@ int stm32mp_uart_console_setup(void)
 
 	reset_uart((uint32_t)dt_uart_info.reset);
 
-	clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
+	clk_rate = (uint32_t)clk_get_rate((unsigned long)dt_uart_info.clock);
 #endif
 
 	set_console(dt_uart_info.base, clk_rate);