Merge changes I6b98eead,Ib4ecae1e into integration

* changes:
  refactor(el3-runtime)!: remove PLAT_PCPU_DATA_SIZE
  fix(el3-runtime): improve PLAT_PCPU_DATA_SIZE check

2 files changed, 1 insertions, 26 deletions

diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 3372c1e0a..67d7769f4 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -515,17 +515,6 @@ must also be defined:
    With this macro, multiple block devices could be supported at the same
    time.
 
-If the platform needs to allocate data within the per-cpu data framework in
-BL31, it should define the following macro. Currently this is only required if
-the platform decides not to use the coherent memory section by undefining the
-``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
-required memory within the the per-cpu data to minimize wastage.
-
--  **#define : PLAT_PCPU_DATA_SIZE**
-
-   Defines the memory (in bytes) to be reserved within the per-cpu data
-   structure for use by the platform layer.
-
 The following constants are optional. They should be defined when the platform
 memory layout implies some image overlaying like in Arm standard platforms.
 
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 3f9c2f9f4..ef25b3a4d 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -48,13 +48,6 @@
 #define CPU_DATA_CPU_DATA_PMF_TS_SIZE	0
 #define CPU_DATA_CPU_DATA_PMF_TS_ALIGN	1
 #endif /* ENABLE_RUNTIME_INSTRUMENTATION */
-#ifdef PLAT_PCPU_DATA_SIZE
-#define CPU_DATA_PLATFORM_CPU_DATA_SIZE	PLAT_PCPU_DATA_SIZE
-#define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1
-#else /* PLAT_PCPU_DATA_SIZE */
-#define CPU_DATA_PLATFORM_CPU_DATA_SIZE	0
-#define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1
-#endif /* PLAT_PCPU_DATA_SIZE */
 #if EL3_EXCEPTION_HANDLING
 /* buffer space for EHF data is sizeof(pe_exc_data_t) */
 #define CPU_DATA_EHF_DATA_SIZE		8
@@ -80,8 +73,7 @@
 #define CPU_DATA_PSCI_SVC_CPU_DATA	ROUND_UP_2EVAL((CPU_DATA_CPU_OPS_PTR + CPU_DATA_CPU_OPS_PTR_SIZE), CPU_DATA_PSCI_SVC_CPU_DATA_ALIGN)
 #define CPU_DATA_APIAKEY		ROUND_UP_2EVAL((CPU_DATA_PSCI_SVC_CPU_DATA + CPU_DATA_PSCI_SVC_CPU_DATA_SIZE), CPU_DATA_APIAKEY_ALIGN)
 #define CPU_DATA_CPU_DATA_PMF_TS	ROUND_UP_2EVAL((CPU_DATA_APIAKEY + CPU_DATA_APIAKEY_SIZE), CPU_DATA_CPU_DATA_PMF_TS_ALIGN)
-#define CPU_DATA_PLATFORM_CPU_DATA	ROUND_UP_2EVAL((CPU_DATA_CPU_DATA_PMF_TS + CPU_DATA_CPU_DATA_PMF_TS_SIZE), CPU_DATA_PLATFORM_CPU_DATA_ALIGN)
-#define CPU_DATA_EHF_DATA		ROUND_UP_2EVAL((CPU_DATA_PLATFORM_CPU_DATA + CPU_DATA_PLATFORM_CPU_DATA_SIZE), CPU_DATA_EHF_DATA_ALIGN)
+#define CPU_DATA_EHF_DATA		ROUND_UP_2EVAL((CPU_DATA_CPU_DATA_PMF_TS + CPU_DATA_CPU_DATA_PMF_TS_SIZE), CPU_DATA_EHF_DATA_ALIGN)
 #define CPU_DATA_PCPU_IDREGS		ROUND_UP_2EVAL((CPU_DATA_EHF_DATA + CPU_DATA_EHF_DATA_SIZE), CPU_DATA_PCPU_IDREGS_ALIGN)
 #define CPU_DATA_SIZE			ROUND_UP_2EVAL((CPU_DATA_PCPU_IDREGS + CPU_DATA_PCPU_IDREGS_SIZE), CPU_DATA_SIZE_ALIGN)
 
@@ -132,9 +124,6 @@ typedef struct cpu_data {
 #if ENABLE_RUNTIME_INSTRUMENTATION
 	uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
 #endif
-#if PLAT_PCPU_DATA_SIZE
-	uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
-#endif
 #if EL3_EXCEPTION_HANDLING
 	pe_exc_data_t ehf_data;
 #endif
@@ -160,9 +149,6 @@ CPU_DATA_ASSERT_OFFSET(APIAKEY, apiakey);
 #if ENABLE_RUNTIME_INSTRUMENTATION
 CPU_DATA_ASSERT_OFFSET(CPU_DATA_PMF_TS, cpu_data_pmf_ts);
 #endif
-#if PLAT_PCPU_DATA_SIZE
-CPU_DATA_ASSERT_OFFSET(PLATFORM_CPU_DATA, platform_cpu_data);
-#endif
 #if EL3_EXCEPTION_HANDLING
 CPU_DATA_ASSERT_OFFSET(EHF_DATA, ehf_data);
 #endif