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| author | Harrison Mutai <harrison.mutai@arm.com> | 2026-06-30 15:41:08 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2026-06-30 15:41:08 +0000 |
| commit | a0b0452186ef40ee5dee6de35fc3bfacbf2efe10 (patch) | |
| tree | bc7a4e0b20f020e1b18c30660832236a80c1e6aa | |
| parent | 365bbb200226cbfd46363978b296224cdbf0fc96 (diff) | |
| parent | f2f23d2535ecc0d79d3e451272d946aeb542d0bd (diff) | |
| download | arm-trusted-firmware-a0b0452186ef40ee5dee6de35fc3bfacbf2efe10.tar.gz arm-trusted-firmware-a0b0452186ef40ee5dee6de35fc3bfacbf2efe10.zip | |
Merge "refactor(context-mgmt): move ICC_SRE definitions to arch.h file" into integration
| -rw-r--r-- | include/arch/aarch32/arch.h | 9 | ||||
| -rw-r--r-- | include/arch/aarch64/arch.h | 6 | ||||
| -rw-r--r-- | include/drivers/arm/gicv3.h | 6 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 1 |
4 files changed, 15 insertions, 7 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 3f0d3a7d2..0ddad2733 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -80,6 +80,15 @@ #endif /******************************************************************************* + * Definitions for CPU system register interface to GIC + ******************************************************************************/ +/* ICC_SRE bit definitions */ +#define ICC_SRE_EN_BIT BIT_32(3) +#define ICC_SRE_DIB_BIT BIT_32(2) +#define ICC_SRE_DFB_BIT BIT_32(1) +#define ICC_SRE_SRE_BIT BIT_32(0) + +/******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF U(0x000) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 4aa8035f3..4dbf8c0a1 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -124,6 +124,12 @@ #define ICC_EOIR1_EL1 S3_0_c12_c12_1 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 +/* ICC_SRE bit definitions */ +#define ICC_SRE_EN_BIT BIT_32(3) +#define ICC_SRE_DIB_BIT BIT_32(2) +#define ICC_SRE_DFB_BIT BIT_32(1) +#define ICC_SRE_SRE_BIT BIT_32(0) + /******************************************************************************* * Definitions for EL2 system registers for save/restore routine ******************************************************************************/ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 07d632f8f..8669f97f4 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -274,12 +274,6 @@ /******************************************************************************* * GICv3 and 3.1 CPU interface registers & constants ******************************************************************************/ -/* ICC_SRE bit definitions */ -#define ICC_SRE_EN_BIT BIT_32(3) -#define ICC_SRE_DIB_BIT BIT_32(2) -#define ICC_SRE_DFB_BIT BIT_32(1) -#define ICC_SRE_SRE_BIT BIT_32(0) - /* ICC_IGRPEN1_EL3 bit definitions */ #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 7df22dc37..044efa37c 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -18,7 +18,6 @@ #include <common/bl_common.h> #include <common/debug.h> #include <context.h> -#include <drivers/arm/gicv3.h> #include <lib/cpus/cpu_ops.h> #include <lib/cpus/errata.h> #include <lib/el3_runtime/context_mgmt.h> |