Merge branch 'next'HEADmasterWIP/06Jul2026

233 files changed, 8692 insertions, 1324 deletions

diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c
index 2f9557a4170..32535ed6ee0 100644
--- a/board/CZ.NIC/turris_1x/turris_1x.c
+++ b/board/CZ.NIC/turris_1x/turris_1x.c
@@ -42,9 +42,9 @@ int dram_init_banksize(void)
 
 	static_assert(CONFIG_NR_DRAM_BANKS >= 3);
 
-	gd->bd->bi_dram[0].start = gd->ram_base;
-	gd->bd->bi_dram[0].size = get_effective_memsize();
-	size -= gd->bd->bi_dram[0].size;
+	gd->dram[0].start = gd->ram_base;
+	gd->dram[0].size = get_effective_memsize();
+	size -= gd->dram[0].size;
 
 	/* Note: This address space is not mapped via TLB entries in U-Boot */
 
@@ -68,16 +68,16 @@ int dram_init_banksize(void)
 
 	if (size > 0) {
 		/* Free space between PCIe bus 3 MEM and NOR */
-		gd->bd->bi_dram[1].start = 0xc0200000;
-		gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start);
-		size -= gd->bd->bi_dram[1].size;
+		gd->dram[1].start = 0xc0200000;
+		gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start);
+		size -= gd->dram[1].size;
 	}
 
 	if (size > 0) {
 		/* Free space between NOR and NAND */
-		gd->bd->bi_dram[2].start = 0xf0000000;
-		gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start);
-		size -= gd->bd->bi_dram[2].size;
+		gd->dram[2].start = 0xf0000000;
+		gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start);
+		size -= gd->dram[2].size;
 	}
 #else
 	puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n");
@@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd)
 
 	if (!env_get("bootm_low") && !env_get("bootm_size")) {
 		for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) {
-			start[count] = gd->bd->bi_dram[count].start;
-			size[count] = gd->bd->bi_dram[count].size;
+			start[count] = gd->dram[count].start;
+			size[count] = gd->dram[count].size;
 			if (!size[count])
 				break;
 		}
@@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void)
 	size = gd->ram_size;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		size -= gd->bd->bi_dram[i].size;
+		size -= gd->dram[i].size;
 
 	if (size == 0)
 		return;
 
 	e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3);
-	if (e.index < 0 && gd->bd->bi_dram[1].size > 0) {
+	if (e.index < 0 && gd->dram[1].size > 0) {
 		/*
 		 * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller
 		 * is inactive, which is the case for Turris 1.0 boards. So
@@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void)
 		printf("Reserving unused ");
 		print_size(bank_size, "");
 		printf(" of PCIe 3 MEM for DDR RAM\n");
-		gd->bd->bi_dram[1].start -= bank_size;
-		gd->bd->bi_dram[1].size += bank_size;
+		gd->dram[1].start -= bank_size;
+		gd->dram[1].size += bank_size;
 		size -= bank_size;
 		if (size == 0)
 			return;
@@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void)
 		printf("Reserving unused ");
 		print_size(free_size2, "");
 		printf(" of PCIe 2 MEM for DDR RAM\n");
-		gd->bd->bi_dram[i].start = free_start2;
-		gd->bd->bi_dram[i].size = min(size, free_size2);
-		size -= gd->bd->bi_dram[i].start;
+		gd->dram[i].start = free_start2;
+		gd->dram[i].size = min(size, free_size2);
+		size -= gd->dram[i].start;
 		i++;
 		if (size == 0)
 			return;
@@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void)
 		printf("Reserving unused ");
 		print_size(free_size1, "");
 		printf(" of PCIe 1 MEM for DDR RAM\n");
-		gd->bd->bi_dram[i].start = free_start1;
-		gd->bd->bi_dram[i].size = min(size, free_size1);
-		size -= gd->bd->bi_dram[i].size;
+		gd->dram[i].start = free_start1;
+		gd->dram[i].size = min(size, free_size1);
+		size -= gd->dram[i].size;
 		i++;
 		if (size == 0)
 			return;
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 7c3cea22b93..78a6d1094b5 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -111,7 +111,7 @@ void mv_phy_88e1121_init(char *name)
 	/* command to read PHY dev address */
 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 		printf("Err..%s could not read PHY dev address\n",
-			__FUNCTION__);
+			__func__);
 		return;
 	}
 
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index e44b713f96d..c30fca6cffd 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -102,11 +102,6 @@ static bool is_edpu_plus(void)
 		return false;
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int board_init(void)
 {
 	/* adress of boot parameters */
diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile
index f688b549063..87be53321ee 100644
--- a/board/Synology/common/Makefile
+++ b/board/Synology/common/Makefile
@@ -2,4 +2,4 @@
 #
 # Copyright (C) 2021 Phil Sutter <phil@nwl.cc>
 
-obj-$(SUPPORT_PASSING_ATAGS)	+= legacy.o
+obj-$(CONFIG_SUPPORT_PASSING_ATAGS)	+= legacy.o
diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c
index 2e3aa660eaa..5b7d07bc2ee 100644
--- a/board/Synology/common/legacy.c
+++ b/board/Synology/common/legacy.c
@@ -10,6 +10,7 @@
 #include <vsprintf.h>
 #include <env.h>
 #include <net.h>
+#include <asm/io.h>
 #include <asm/setup.h>
 
 #include "legacy.h"
diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env
deleted file mode 100644
index 8b03a3d5da9..00000000000
--- a/board/adi/sc573-ezkit/sc573-ezkit.env
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later+ */
-/*
- * (C) Copyright 2024 - Analog Devices, Inc.
- */
-
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc573-ezkit.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
-
-#define USE_NFS
-#define USE_SPI
-#define USE_RAM
-#define USE_MMC
-
-#include <env/adi/adi_boot.env>
diff --git a/board/adi/sc573-ezkit/Kconfig b/board/adi/sc573-ezlite/Kconfig
index 328563c1296..f3b848ef0f7 100644
--- a/board/adi/sc573-ezkit/Kconfig
+++ b/board/adi/sc573-ezlite/Kconfig
@@ -2,19 +2,19 @@
 #
 # (C) Copyright 2024 - Analog Devices, Inc.
 
-if TARGET_SC573_EZKIT
+if TARGET_SC573_EZLITE
 
 config SYS_BOARD
-	default "sc573-ezkit"
+	default "sc573-ezlite"
 
 config SYS_CONFIG_NAME
-	default "sc573-ezkit"
+	default "sc573-ezlite"
 
 config LDR_CPU
 	default "ADSP-SC573-0.0"
 
 config DEFAULT_DEVICE_TREE
-	default "sc573-ezkit"
+	default "sc573-ezlite"
 
 config ADI_IMAGE
 	default "tiny"
diff --git a/board/adi/sc573-ezkit/Makefile b/board/adi/sc573-ezlite/Makefile
index 0ea725b992b..77c55af6240 100644
--- a/board/adi/sc573-ezkit/Makefile
+++ b/board/adi/sc573-ezlite/Makefile
@@ -3,4 +3,4 @@
 # (C) Copyright 2025 - Analog Devices, Inc.
 #
 
-obj-y	+= sc573-ezkit.o
+obj-y	+= sc573-ezlite.o
diff --git a/board/adi/sc573-ezkit/sc573-ezkit.c b/board/adi/sc573-ezlite/sc573-ezlite.c
index 464142b27a5..464142b27a5 100644
--- a/board/adi/sc573-ezkit/sc573-ezkit.c
+++ b/board/adi/sc573-ezlite/sc573-ezlite.c
diff --git a/board/adi/sc573-ezlite/sc573-ezlite.env b/board/adi/sc573-ezlite/sc573-ezlite.env
new file mode 100644
index 00000000000..bc1fdf293c2
--- /dev/null
+++ b/board/adi/sc573-ezlite/sc573-ezlite.env
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later+ */
+/*
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ */
+
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0x84008000
+ramdisk_addr_r=0x85000000
+
+#define USE_NFS
+#define USE_SPI
+#define USE_RAM
+#define USE_MMC
+#define USE_USB
+
+#include <env/adi/adi_boot.env>
diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env
index 8a6f7edd5e8..ed25fc599a1 100644
--- a/board/adi/sc584-ezkit/sc584-ezkit.env
+++ b/board/adi/sc584-ezkit/sc584-ezkit.env
@@ -3,14 +3,13 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc584-ezkit.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0x8a308000
+ramdisk_addr_r=0x8b300000
 
 #define USE_NFS
 #define USE_SPI
 #define USE_RAM
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env
index b8206e85179..3a1af951260 100644
--- a/board/adi/sc589-ezkit/sc589-ezkit.env
+++ b/board/adi/sc589-ezkit/sc589-ezkit.env
@@ -3,15 +3,14 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-ezkit.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0xc4008000
+ramdisk_addr_r=0xc5000000
 
 #define USE_NFS
 #define USE_RAM
 #define USE_MMC
 #define USE_SPI
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env
index f7628b0b335..a21bb4e2200 100644
--- a/board/adi/sc589-mini/sc589-mini.env
+++ b/board/adi/sc589-mini/sc589-mini.env
@@ -3,15 +3,14 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-mini.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0xc4008000
+ramdisk_addr_r=0xc5000000
 
 #define USE_NFS
 #define USE_RAM
 #define USE_SPI
 #define USE_MMC
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env
index 069edc717da..a8f6def9f58 100644
--- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env
+++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env
@@ -3,16 +3,15 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezkit.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0xa3008000
+ramdisk_addr_r=0xa8000000
 
 #define USE_NFS
 #define USE_SPI
 #define USE_OSPI
 #define USE_RAM
 #define USE_MMC
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env
index e5382b67c81..a8f6def9f58 100644
--- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env
+++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env
@@ -3,16 +3,15 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezlite.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0xa3008000
+ramdisk_addr_r=0xa8000000
 
 #define USE_NFS
 #define USE_SPI
 #define USE_OSPI
 #define USE_RAM
 #define USE_MMC
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env
index 2cb475e1001..da1ff295b0e 100644
--- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env
+++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env
@@ -3,16 +3,15 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezkit.jffs2
-loadaddr=CONFIG_SC5XX_LOADADDR
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0x9a200000
+ramdisk_addr_r=0x9c000000
 
 #define USE_NFS
 #define USE_SPI
 #define USE_OSPI
 #define USE_RAM
 #define USE_MMC
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env
index 1d9ea6d188b..3f65fdabe18 100644
--- a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env
+++ b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env
@@ -3,10 +3,14 @@
  * (C) Copyright 2024 - Analog Devices, Inc.
  */
 
-adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET
-adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET
-adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET
-loadaddr=CONFIG_SC5XX_LOADADDR
-jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezlite.jffs2
+fdt_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_addr_r=0x9a200000
+ramdisk_addr_r=0x9c000000
+
+#define USE_NFS
+#define USE_SPI
+#define USE_RAM
+#define USE_MMC
+#define USE_USB
 
 #include <env/adi/adi_boot.env>
diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig
index 5c2609b7f46..49516b7f007 100644
--- a/board/alliedtelesis/SBx81LIFKW/Kconfig
+++ b/board/alliedtelesis/SBx81LIFKW/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
        default "SBx81LIFKW"
 
 config SYS_VENDOR
-       default "alliedtelesis"
+	default "alliedtelesis"
 
 config SYS_CONFIG_NAME
        default "SBx81LIFKW"
diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
index 524c2900892..20e02144d3a 100644
--- a/board/alliedtelesis/SBx81LIFXCAT/Kconfig
+++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
        default "SBx81LIFXCAT"
 
 config SYS_VENDOR
-       default "alliedtelesis"
+	default "alliedtelesis"
 
 config SYS_CONFIG_NAME
        default "SBx81LIFXCAT"
diff --git a/board/alliedtelesis/x220/.gitattributes b/board/alliedtelesis/x220/.gitattributes
new file mode 100644
index 00000000000..2aeb4eee641
--- /dev/null
+++ b/board/alliedtelesis/x220/.gitattributes
@@ -0,0 +1 @@
+binary.0 binary
diff --git a/board/alliedtelesis/x220/.gitignore b/board/alliedtelesis/x220/.gitignore
new file mode 100644
index 00000000000..775b9346b85
--- /dev/null
+++ b/board/alliedtelesis/x220/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/board/alliedtelesis/x220/MAINTAINERS b/board/alliedtelesis/x220/MAINTAINERS
new file mode 100644
index 00000000000..63da2725f71
--- /dev/null
+++ b/board/alliedtelesis/x220/MAINTAINERS
@@ -0,0 +1,8 @@
+x220 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x220
+F:	include/configs/x220.h
+F:	configs/x220_defconfig
+F:	arch/arm/dts/armada-xp-atl-x220.dts
+F:	doc/board/alliedtelesis/x220.rst
diff --git a/board/alliedtelesis/x220/Makefile b/board/alliedtelesis/x220/Makefile
new file mode 100644
index 00000000000..a74f0a76948
--- /dev/null
+++ b/board/alliedtelesis/x220/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Allied Telesis Labs
+
+obj-y	:= x220.o
+extra-y	:= kwbimage.cfg
+
+quiet_cmd_sed = SED     $@
+      cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	  $(call if_changed,sed)
diff --git a/board/alliedtelesis/x220/binary.0 b/board/alliedtelesis/x220/binary.0
new file mode 100644
index 00000000000..8dd687286a0
--- /dev/null
+++ b/board/alliedtelesis/x220/binary.0
@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/board/alliedtelesis/x220/kwbimage.cfg.in b/board/alliedtelesis/x220/kwbimage.cfg.in
new file mode 100644
index 00000000000..8beda907ba4
--- /dev/null
+++ b/board/alliedtelesis/x220/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2025 Allied Telesis Labs
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/alliedtelesis/x220/binary.0 0000005b 00000068
diff --git a/board/alliedtelesis/x220/x220.c b/board/alliedtelesis/x220/x220.c
new file mode 100644
index 00000000000..7c9a73de9a2
--- /dev/null
+++ b/board/alliedtelesis/x220/x220.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Allied Telesis Labs
+ */
+
+#include <i2c.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define X220_GPP_OUT_ENA_LOW	(~(BIT(12) | BIT(17) | BIT(18) | BIT(31)))
+#define X220_GPP_OUT_ENA_MID	(~(0))
+#define X220_GPP_OUT_VAL_LOW	(BIT(12) | BIT(18))
+#define X220_GPP_OUT_VAL_MID	0x0
+#define X220_GPP_POL_LOW	0x0
+#define X220_GPP_POL_MID	0x0
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x44042222, MVEBU_MPP_BASE + 0x00);
+	writel(0x11000004, MVEBU_MPP_BASE + 0x04);
+	writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+	writel(0x04444444, MVEBU_MPP_BASE + 0x0c);
+	writel(0x00000004, MVEBU_MPP_BASE + 0x10);
+
+	/* Set GPP Out value */
+	writel(X220_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(X220_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(X220_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(X220_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(X220_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(X220_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Disable MBUS Err Prop - in order to avoid data aborts */
+	clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: Allied Telesis x220\n");
+
+	return 0;
+}
+#endif
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c
index 81daba1c5ef..ec28e60c410 100644
--- a/board/amd/versal2/board.c
+++ b/board/amd/versal2/board.c
@@ -1,17 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
 
 #include <cpu_func.h>
+#include <dfu.h>
+#include <env.h>
+#include <efi_loader.h>
 #include <fdtdec.h>
+#include <fwu.h>
 #include <init.h>
 #include <env_internal.h>
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
+#include <mmc.h>
+#include <mtd.h>
 #include <time.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
@@ -26,6 +33,7 @@
 #include "../../xilinx/common/board.h"
 
 #include <linux/bitfield.h>
+#include <linux/sizes.h>
 #include <debug_uart.h>
 #include <generated/dt.h>
 #include <linux/ioport.h>
@@ -348,6 +356,10 @@ int board_late_init(void)
 	int ret;
 	u32 multiboot;
 
+	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) &&
+	    !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE))
+		configure_capsule_updates();
+
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 		debug("Saved variables - Skipping\n");
 		return 0;
@@ -476,3 +488,120 @@ enum env_location env_get_location(enum env_operation op, int prio)
 	}
 }
 #endif
+
+#define DFU_ALT_BUF_LEN		SZ_1K
+
+#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \
+	!defined(CONFIG_FWU_MULTI_BANK_UPDATE)
+static void mtd_found_part(u32 *base, u32 *size)
+{
+	struct mtd_info *part, *mtd;
+
+	mtd_probe_devices();
+
+	mtd = get_mtd_device_nm("nor0");
+	if (!IS_ERR_OR_NULL(mtd)) {
+		list_for_each_entry(part, &mtd->partitions, node) {
+			debug("0x%012llx-0x%012llx : \"%s\"\n",
+			      part->offset, part->offset + part->size,
+			      part->name);
+
+			if (*base >= part->offset &&
+			    *base < part->offset + part->size) {
+				debug("Found my partition: %d/%s\n",
+				      part->index, part->name);
+				*base = part->offset;
+				*size = part->size;
+				break;
+			}
+		}
+	}
+}
+
+void configure_capsule_updates(void)
+{
+	int bootseq = 0, len = 0;
+	u32 multiboot = versal2_multi_boot();
+	u32 bootmode = versal2_get_bootmode();
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	memset(buf, 0, DFU_ALT_BUF_LEN);
+
+	multiboot = env_get_hex("multiboot", multiboot);
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		bootseq = mmc_get_env_dev();
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
+			       bootseq);
+
+		if (multiboot)
+			len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+					"%04d", multiboot);
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
+			       bootseq);
+		break;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+	case OSPI_MODE:
+		{
+			u32 base = multiboot * SZ_32K;
+			u32 size = 0x1500000;
+			u32 limit = size;
+
+			mtd_found_part(&base, &limit);
+
+			len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+					"sf 0:0=boot.bin raw 0x%x 0x%x",
+					base, limit);
+		}
+		break;
+	default:
+		return;
+	}
+
+	update_info.dfu_string = strdup(buf);
+	debug("Capsule DFU: %s\n", update_info.dfu_string);
+}
+#endif
+
+#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	int ret;
+	struct mtd_info *mtd;
+
+	/*
+	 * It is called multiple times for every image
+	 * per bank that's why enough to set it up once.
+	 */
+	if (env_get("dfu_alt_info"))
+		return;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+	memset(buf, 0, DFU_ALT_BUF_LEN);
+
+	mtd_probe_devices();
+
+	mtd = get_mtd_device_nm("nor0");
+	if (IS_ERR_OR_NULL(mtd))
+		return;
+
+	ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+	if (ret < 0) {
+		log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret);
+		return;
+	}
+	log_debug("Make dfu_alt_info: '%s'\n", buf);
+
+	env_set("dfu_alt_info", buf);
+}
+#endif
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 8cfac9fbb34..4a2349e165b 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -218,7 +218,7 @@ static void set_gpr_register(void)
 
 int board_early_init_f(void)
 {
-	select_ldb_di_clock_source(MXC_PLL5_CLK);
+	select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
 	set_gpr_register();
 
 	/*
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
index 16d0e679c3e..eb0f9c06849 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -86,8 +86,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index eaf87e3bfe3..6cd24bf25fb 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -137,7 +137,7 @@ int misc_init_r (void)
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
 #ifdef CONFIG_CM_SPD_DETECT
 	{
 extern void dram_query(void);
@@ -170,7 +170,7 @@ extern void dram_query(void);
 				    PHYS_SDRAM_1_SIZE);
 #endif /* CM_SPD_DETECT */
 	/* We only have one bank of RAM, set it to whatever was detected */
-	gd->bd->bi_dram[0].size	 = gd->ram_size;
+	gd->dram[0].size	 = gd->ram_size;
 
 	return 0;
 }
diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c
index 12bb6defab2..057e916ab1b 100644
--- a/board/armltd/total_compute/total_compute.c
+++ b/board/armltd/total_compute/total_compute.c
@@ -89,9 +89,9 @@ void build_mem_map(void)
 		 * The first node is for I/O device, start from node 1 for
 		 * updating DRAM info.
 		 */
-		mem_map[i + 1].virt = gd->bd->bi_dram[i].start;
-		mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
-		mem_map[i + 1].size = gd->bd->bi_dram[i].size;
+		mem_map[i + 1].virt = gd->dram[i].start;
+		mem_map[i + 1].phys = gd->dram[i].start;
+		mem_map[i + 1].size = gd->dram[i].size;
 		mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 				       PTE_BLOCK_INNER_SHARE;
 	}
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index 3833af59b09..87e53f64e06 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -79,11 +79,11 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size =
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size =
 			get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size =
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size =
 			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 
 	return 0;
diff --git a/board/aspeed/evb_ast2700/Kconfig b/board/aspeed/evb_ast2700/Kconfig
new file mode 100644
index 00000000000..ede9eb7fb85
--- /dev/null
+++ b/board/aspeed/evb_ast2700/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_EVB_AST2700
+
+config SYS_BOARD
+	default "evb_ast2700"
+
+config SYS_VENDOR
+	default "aspeed"
+
+config SYS_CONFIG_NAME
+	string "board configuration name"
+	default "evb_ast2700"
+
+endif
diff --git a/board/aspeed/evb_ast2700/Makefile b/board/aspeed/evb_ast2700/Makefile
new file mode 100644
index 00000000000..0c29700f5a9
--- /dev/null
+++ b/board/aspeed/evb_ast2700/Makefile
@@ -0,0 +1 @@
+obj-y += evb_ast2700.o
diff --git a/board/aspeed/evb_ast2700/evb_ast2700.c b/board/aspeed/evb_ast2700/evb_ast2700.c
new file mode 100644
index 00000000000..b34aa6e1682
--- /dev/null
+++ b/board/aspeed/evb_ast2700/evb_ast2700.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c
index 77188820581..7cb492b2da6 100644
--- a/board/atmel/common/video_display.c
+++ b/board/atmel/common/video_display.c
@@ -40,7 +40,7 @@ int at91_video_show_board_info(void)
 
 	dram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		dram_size += gd->bd->bi_dram[i].size;
+		dram_size += gd->dram[i].size;
 
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
index 43797d625e9..b19ae3b4b03 100644
--- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
+++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
@@ -66,7 +66,7 @@ int misc_init_r(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	board_leds_init();
 
diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c
index 364b6a3e24b..5c35239a90a 100644
--- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c
+++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c
@@ -45,7 +45,7 @@ void board_debug_uart_init(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	return 0;
 }
diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
index 858061bf9f9..33ae6a76bf7 100644
--- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
+++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
@@ -64,7 +64,7 @@ void board_debug_uart_init(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	rgb_leds_init();
 
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index 19341d325bd..0e2d5592753 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -58,7 +58,7 @@ void board_debug_uart_init(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	rgb_leds_init();
 
diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
index 8759ff6f01a..1a17db1bd5b 100644
--- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
+++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
@@ -65,7 +65,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	rgb_leds_init();
 
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index c0862f58606..b48e8fe7697 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -63,7 +63,7 @@ void board_debug_uart_init(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	rgb_leds_init();
 
diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
index 764c8f035c9..cdf2793b643 100644
--- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
+++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
@@ -52,7 +52,7 @@ void board_debug_uart_init(void)
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	board_leds_init();
 
diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
index b05c9754c96..02543d8e99f 100644
--- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
+++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
 	// Address of boot parameters
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	return 0;
 }
diff --git a/board/axiado/scm3005/Kconfig b/board/axiado/scm3005/Kconfig
new file mode 100644
index 00000000000..d6f4f311f55
--- /dev/null
+++ b/board/axiado/scm3005/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SCM3005
+
+config SYS_BOARD
+	string
+	default "scm3005"
+
+config SYS_VENDOR
+	string
+	default "axiado"
+
+config SYS_CONFIG_NAME
+	string
+	default "ax3005-scm3005"
+
+endif
diff --git a/board/axiado/scm3005/Makefile b/board/axiado/scm3005/Makefile
new file mode 100644
index 00000000000..3d35713bab9
--- /dev/null
+++ b/board/axiado/scm3005/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+
+obj-y := scm3005.o
diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c
new file mode 100644
index 00000000000..b2df6d89cd8
--- /dev/null
+++ b/board/axiado/scm3005/scm3005.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/spin_table.h>
+#include <asm/system.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region axiado_ax3005_mem_map[] = {
+	{ /* Peripherals including UART */
+	  .virt = 0x00000000UL,
+	  .phys = 0x00000000UL,
+	  .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */
+	  .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
+		   PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	{ .virt = 0x80000000UL,
+	  .phys = 0x80000000UL,
+	  .size = 0x80000000UL,
+	  .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE },
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = axiado_ax3005_mem_map;
+
+/*
+ * Accept any FIT configuration name - the board loads a single FIT image
+ * and the first matching config is used.
+ */
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+
+/*
+ * ft_board_setup - restore cpu-release-addr after relocation
+ *
+ * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr
+ * with U-Boot's relocated address.  Restore the pre-relocation physical
+ * address so secondary cores spin on the correct location.
+ */
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int cpus_offset, offset;
+	const char *prop;
+	int ret;
+	u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off;
+
+	cpus_offset = fdt_path_offset(blob, "/cpus");
+	if (cpus_offset < 0)
+		return 0;
+
+	for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0;
+	     offset = fdt_next_subnode(blob, offset)) {
+		prop = fdt_getprop(blob, offset, "device_type", NULL);
+		if (!prop || strcmp(prop, "cpu"))
+			continue;
+
+		prop = fdt_getprop(blob, offset, "enable-method", NULL);
+		if (!prop || strcmp(prop, "spin-table"))
+			continue;
+
+		ret = fdt_setprop_u64(blob, offset, "cpu-release-addr",
+				      cpu_release_addr);
+		if (ret) {
+			printf("WARNING: Failed to restore cpu-release-addr\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * dram_init - DDR is initialized by firmware, just setting size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/*
+ * the SOC uses single bank, non-interleaving
+ */
+int dram_init_banksize(void)
+{
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+/*
+ * timer_init - enable the AX3005 platform system timer
+ *
+ * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using
+ * CONFIG_COUNTER_FREQUENCY from the defconfig.
+ *
+ * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control
+ * register — writing SYS_TIMER_ENABLE starts the counter that feeds
+ * the ARM generic timer.
+ */
+int timer_init(void)
+{
+	writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	/* For later ARM_PSCI_FW or watchdog reset */
+}
diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig
index 0f21582614d..7d7077e9f28 100644
--- a/board/beagle/beagleboneai64/Kconfig
+++ b/board/beagle/beagleboneai64/Kconfig
@@ -34,7 +34,7 @@ config SYS_BOARD
        default "beagleboneai64"
 
 config SYS_VENDOR
-       default "beagle"
+	default "beagle"
 
 config SYS_CONFIG_NAME
        default "beagleboneai64"
@@ -49,7 +49,7 @@ config SYS_BOARD
        default "beagleboneai64"
 
 config SYS_VENDOR
-       default "beagle"
+	default "beagle"
 
 config SYS_CONFIG_NAME
        default "beagleboneai64"
diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig
index 592b53e493c..fcc6a5aa496 100644
--- a/board/beagle/beagleplay/Kconfig
+++ b/board/beagle/beagleplay/Kconfig
@@ -30,13 +30,13 @@ endchoice
 if TARGET_AM625_A53_BEAGLEPLAY
 
 config SYS_BOARD
-       default "beagleplay"
+	default "beagleplay"
 
 config SYS_VENDOR
-       default "beagle"
+	default "beagle"
 
 config SYS_CONFIG_NAME
-       default "beagleplay"
+	default "beagleplay"
 
 source "board/ti/common/Kconfig"
 
@@ -45,13 +45,13 @@ endif
 if TARGET_AM625_R5_BEAGLEPLAY
 
 config SYS_BOARD
-       default "beagleplay"
+	default "beagleplay"
 
 config SYS_VENDOR
-       default "beagle"
+	default "beagle"
 
 config SYS_CONFIG_NAME
-       default "beagleplay"
+	default "beagleplay"
 
 config SPL_LDSCRIPT
 	default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/beagle/beagley-ai/Kconfig b/board/beagle/beagley-ai/Kconfig
index bf953982151..07aedc2ea3f 100644
--- a/board/beagle/beagley-ai/Kconfig
+++ b/board/beagle/beagley-ai/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "beagley-ai"
 
 config SYS_VENDOR
-       default "beagle"
+	default "beagle"
 
 config SYS_CONFIG_NAME
        default "beagley_ai"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 1adee9a461f..e45db109f4f 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -909,8 +909,10 @@ static const struct boot_mode board_boot_modes[] = {
 
 int misc_init_r(void)
 {
+#if defined(CONFIG_VIDEO_IPUV3)
 	gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
 	gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
+#endif
 	gpio_request(GP_USB_OTG_PWR, "usbotg power");
 	gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
 	gpio_request(IMX_GPIO_NR(2, 2), "back");
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index bb2f1e4f62a..2683f46f41c 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -176,8 +176,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
-	gd->bd->bi_dram[0].size = SZ_16M;
+	gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+	gd->dram[0].size = SZ_16M;
 
 	return 0;
 }
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 40047cf6783..5bc4d3248bd 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -666,34 +666,34 @@ int misc_init_r(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[1].start = PHYS_SDRAM_2;
 
 	switch (gd->ram_size) {
 	case 0x10000000: /* DDR_16BIT_256MB */
-		gd->bd->bi_dram[0].size = 0x10000000;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[0].size = 0x10000000;
+		gd->dram[1].size = 0;
 		break;
 	case 0x20000000: /* DDR_32BIT_512MB */
-		gd->bd->bi_dram[0].size = 0x20000000;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[0].size = 0x20000000;
+		gd->dram[1].size = 0;
 		break;
 	case 0x40000000:
 		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
-			gd->bd->bi_dram[0].size = 0x20000000;
-			gd->bd->bi_dram[1].size = 0x20000000;
+			gd->dram[0].size = 0x20000000;
+			gd->dram[1].size = 0x20000000;
 		} else { /* DDR_64BIT_1GB */
-			gd->bd->bi_dram[0].size = 0x40000000;
-			gd->bd->bi_dram[1].size = 0;
+			gd->dram[0].size = 0x40000000;
+			gd->dram[1].size = 0;
 		}
 		break;
 	case 0x80000000: /* DDR_64BIT_2GB */
-		gd->bd->bi_dram[0].size = 0x40000000;
-		gd->bd->bi_dram[1].size = 0x40000000;
+		gd->dram[0].size = 0x40000000;
+		gd->dram[1].size = 0x40000000;
 		break;
 	case 0xEFF00000: /* DDR_64BIT_4GB */
-		gd->bd->bi_dram[0].size = 0x70000000;
-		gd->bd->bi_dram[1].size = 0x7FF00000;
+		gd->dram[0].size = 0x70000000;
+		gd->dram[1].size = 0x7FF00000;
 		break;
 	}
 
@@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev)
 	return 0;
 }
 
-struct ahci_ops sata_imx_ops = {
+static const struct ahci_ops sata_imx_ops = {
 	.port_status = dwc_ahsata_port_status,
 	.reset	= dwc_ahsata_bus_reset,
 	.scan	= dwc_ahsata_scan,
diff --git a/board/cortina/common/Kconfig b/board/cortina/common/Kconfig
index 00c709e70f0..bf5229abd75 100644
--- a/board/cortina/common/Kconfig
+++ b/board/cortina/common/Kconfig
@@ -1,6 +1,6 @@
 config CORTINA_PLATFORM
-       bool "Cortina-Access Platform"
-       default y
-       help
-         Select this option for Cortina-Access platforms
-	 to enables selection of CAxxxx drivers
+	bool "Cortina-Access Platform"
+	default y
+	help
+	  Select this option for Cortina-Access platforms
+	  to enables selection of CAxxxx drivers
diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig
index 8e6f6cfa27c..7bf8b78742a 100644
--- a/board/cortina/presidio-asic/Kconfig
+++ b/board/cortina/presidio-asic/Kconfig
@@ -1,7 +1,7 @@
 if TARGET_PRESIDIO_ASIC
 config BIT64
        bool
-       default y
+	default y
 
 select SOC_CA7774
 
diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c
index 9fea4f86d5a..33f7ec6d048 100644
--- a/board/elgin/elgin_rv1108/elgin_rv1108.c
+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -66,8 +66,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = 0x60000000;
-	gd->bd->bi_dram[0].size = 0x8000000;
+	gd->dram[0].start = 0x60000000;
+	gd->dram[0].size = 0x8000000;
 
 	return 0;
 }
diff --git a/board/emulation/qemu-m68k/qemu-m68k.c b/board/emulation/qemu-m68k/qemu-m68k.c
index d3527aee112..a19b23a28ce 100644
--- a/board/emulation/qemu-m68k/qemu-m68k.c
+++ b/board/emulation/qemu-m68k/qemu-m68k.c
@@ -14,9 +14,14 @@
 #include <asm/bootinfo.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
 #include <dm/platdata.h>
+#include <dm/root.h>
 #include <linux/errno.h>
 #include <linux/sizes.h>
+#include <virtio_mmio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,6 +30,38 @@ static struct goldfish_rtc_plat rtc_plat;
 static struct goldfish_timer_plat timer_plat;
 static struct qemu_virt_ctrl_plat reset_plat;
 
+#define VIRTIO_MMIO_NUM	128
+#define VIRTIO_MMIO_SZ	0x200
+
+static struct virtio_mmio_plat virtio_mmio_plat[VIRTIO_MMIO_NUM];
+static char virtio_mmio_names[VIRTIO_MMIO_NUM][11];
+static phys_addr_t virtio_mmio_base;
+
+static int create_virtio_mmios(void)
+{
+	struct driver *drv;
+	int i, ret;
+
+	if (!virtio_mmio_base)
+		return -ENODEV;
+
+	drv = lists_driver_lookup_name("virtio-mmio");
+	if (!drv)
+		return -ENOENT;
+
+	for (i = 0; i < VIRTIO_MMIO_NUM; i++) {
+		virtio_mmio_plat[i].base = virtio_mmio_base + (VIRTIO_MMIO_SZ * i);
+		sprintf(virtio_mmio_names[i], "virtio-%d", i);
+
+		ret = device_bind(dm_root(), drv, virtio_mmio_names[i],
+				  &virtio_mmio_plat[i], ofnode_null(), NULL);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 /*
  * Theoretical limit derivation:
  * Max Bootinfo Size (Standard Page) = 4096 bytes
@@ -65,6 +102,9 @@ static void parse_bootinfo(void)
 		case BI_VIRT_CTRL_BASE:
 			reset_plat.reg = base;
 			break;
+		case BI_VIRT_VIRTIO_BASE:
+			virtio_mmio_base = base;
+			break;
 		case BI_MEMCHUNK:
 			gd->ram_size = record->data[1];
 			break;
@@ -80,6 +120,11 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int board_early_init_r(void)
+{
+	return create_virtio_mmios();
+}
+
 int checkboard(void)
 {
 	puts("Board: QEMU m68k virt\n");
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index dce69abdfd1..3d76c936073 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -141,8 +141,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->dram[0].start = PHYS_SDRAM;
+	gd->dram[0].size = PHYS_SDRAM_SIZE;
 
 	return 0;
 }
diff --git a/board/firefly/roc-pc-rk3399/Kconfig b/board/firefly/roc-pc-rk3399/Kconfig
index c211e9d3c79..b800f7d2102 100644
--- a/board/firefly/roc-pc-rk3399/Kconfig
+++ b/board/firefly/roc-pc-rk3399/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
         default "roc-pc-rk3399"
 
 config SYS_VENDOR
-        default "firefly"
+	default "firefly"
 
 config SYS_CONFIG_NAME
         default "roc-pc-rk3399"
diff --git a/board/freebox/nbx10g/Kconfig b/board/freebox/nbx10g/Kconfig
new file mode 100644
index 00000000000..958c8fdd4c3
--- /dev/null
+++ b/board/freebox/nbx10g/Kconfig
@@ -0,0 +1,94 @@
+if TARGET_NBX10G
+
+config SYS_BOARD
+	default "nbx10g"
+
+config SYS_VENDOR
+	default "freebox"
+
+config SYS_CONFIG_NAME
+	default "nbx10g"
+
+config CMD_NBX_EMMCBOOT
+	bool "emmcboot command"
+	depends on MMC_SDHCI_XENON
+	help
+	  Enable the emmcboot command for dual-bank boot from eMMC.
+	  This is a legacy boot format used on this board for many years.
+	  It implements a boot system with two image banks and automatic
+	  fallback on boot failures. The boot order depends on a reboot
+	  tracking counter (nrboot):
+	  - If healthy: try Bank1 (newer) first, then Bank0 (stable)
+	  - If degraded (>= 4 failures): try Bank0 first, then Bank1
+
+	  Requires image_addr and fdt_addr environment variables to be set.
+
+if CMD_NBX_EMMCBOOT
+
+config NBX_MMC_PART_NRBOOT_OFFSET
+	hex "NRBoot counter offset in eMMC"
+	default 0x802000
+	help
+	  Byte offset in eMMC where the reboot tracking counter is stored.
+	  Default: 0x802000 (8MB + 8KB)
+
+config NBX_MMC_PART_BANK0_OFFSET
+	hex "Bank0 image offset in eMMC"
+	default 0x804000
+	help
+	  Byte offset in eMMC where the stable (Bank0) boot image starts.
+	  Default: 0x804000 (8MB + 16KB)
+
+config NBX_MMC_PART_BANK0_SIZE
+	hex "Bank0 image maximum size"
+	default 0x10000000
+	help
+	  Maximum size of the Bank0 boot image.
+	  Default: 0x10000000 (256MB)
+
+config NBX_MMC_PART_BANK1_OFFSET
+	hex "Bank1 image offset in eMMC"
+	default 0x10804000
+	help
+	  Byte offset in eMMC where the newer (Bank1) boot image starts.
+	  Default: 0x10804000 (264MB + 16KB)
+
+config NBX_MMC_PART_BANK1_SIZE
+	hex "Bank1 image maximum size"
+	default 0x10000000
+	help
+	  Maximum size of the Bank1 boot image.
+	  Default: 0x10000000 (256MB)
+
+endif
+
+config CMD_NBX_FBXSERIAL
+	bool "fbxserial command"
+	depends on MMC_SDHCI_XENON
+	help
+	  Enable the fbxserial command to read and display device
+	  serial information from eMMC. This includes:
+	  - Device serial number (type, version, manufacturer, date, number)
+	  - MAC address (used to set ethaddr environment variables)
+	  - Bundle information (if present)
+
+	  The serial info is stored at a fixed offset in the eMMC user area.
+
+	  Subcommands:
+	  - fbxserial show: display serial info (default)
+	  - fbxserial init: initialize ethaddr from serial info
+
+	  Use CONFIG_PREBOOT="fbxserial init" to auto-initialize at boot.
+
+if CMD_NBX_FBXSERIAL
+
+config NBX_MMC_PART_SERIAL_OFFSET
+	hex "Serial info offset in eMMC"
+	default 0x800000
+	help
+	  Byte offset in eMMC where the serial info structure is stored.
+	  Default: 0x800000 (8MB)
+
+endif
+
+endif
diff --git a/board/freebox/nbx10g/MAINTAINERS b/board/freebox/nbx10g/MAINTAINERS
new file mode 100644
index 00000000000..2e31eed45b9
--- /dev/null
+++ b/board/freebox/nbx10g/MAINTAINERS
@@ -0,0 +1,6 @@
+NBX10G BOARD
+M:	Vincent Jardin <vjardin@free.fr>
+S:	Maintained
+F:	board/freebox/nbx10g/
+F:	configs/mvebu_nbx_88f8040_defconfig
+F:	arch/arm/dts/armada-8040-nbx*
diff --git a/board/freebox/nbx10g/Makefile b/board/freebox/nbx10g/Makefile
new file mode 100644
index 00000000000..4b70d94e14d
--- /dev/null
+++ b/board/freebox/nbx10g/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= board.o
+obj-$(CONFIG_CMD_NBX_EMMCBOOT)	+= nbx_emmcboot.o
+obj-$(CONFIG_CMD_NBX_FBXSERIAL)	+= nbx_fbxserial.o
diff --git a/board/freebox/nbx10g/board.c b/board/freebox/nbx10g/board.c
new file mode 100644
index 00000000000..7d16010ec7e
--- /dev/null
+++ b/board/freebox/nbx10g/board.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2018 Freebox SA
+ * Copyright (C) 2026 Free Mobile, Vincent Jardin <vjardin@free.fr>
+ *
+ * Freebox Nodebox 10G board support
+ */
+
+#include <init.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+/* Management PHY reset GPIO */
+#define NBX_PHY_RESET_GPIO	83
+
+/* Nodebox 10G ASCII art logo */
+static const char * const nbx_logo =
+	"  _   _           _      _                 __  ___   _____\n"
+	" | \\ | |         | |    | |               /_ |/ _ \\ / ____|\n"
+	" |  \\| | ___   __| | ___| |__   _____  __  | | | | | |  __\n"
+	" | . ` |/ _ \\ / _` |/ _ \\ '_ \\ / _ \\ \\/ /  | | | | | | |_ |\n"
+	" | |\\  | (_) | (_| |  __/ |_) | (_) >  <   | | |_| | |__| |\n"
+	" |_| \\_|\\___/ \\__,_|\\___|_.__/ \\___/_/\\_\\  |_|\\___/ \\_____|\n";
+
+int checkboard(void)
+{
+	printf("%s\n", nbx_logo);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int ret;
+
+	/* Reset the management PHY */
+	ret = gpio_request(NBX_PHY_RESET_GPIO, "phy-reset");
+	if (ret) {
+		printf("Failed to request PHY reset GPIO: %d\n", ret);
+		return 0;
+	}
+
+	gpio_direction_output(NBX_PHY_RESET_GPIO, 0);
+	mdelay(100);
+	gpio_set_value(NBX_PHY_RESET_GPIO, 1);
+	mdelay(100);
+
+	return 0;
+}
diff --git a/board/freebox/nbx10g/nbx_emmcboot.c b/board/freebox/nbx10g/nbx_emmcboot.c
new file mode 100644
index 00000000000..0bea96fadd9
--- /dev/null
+++ b/board/freebox/nbx10g/nbx_emmcboot.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Nodebox 10G dual-bank eMMC boot command with automatic fallback
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ *
+ * This implements a dual-bank boot system with automatic fallback:
+ * - Bank0: Stable/fallback boot image
+ * - Bank1: Newer/test boot image
+ *
+ * The boot order depends on the reboot tracking counter (nrboot):
+ * - If healthy: try Bank1 first, then Bank0
+ * - If degraded (>= 4 failures): try Bank0 first, then Bank1
+ */
+
+#include <command.h>
+#include <env.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <vsprintf.h>
+#include <u-boot/crc.h>
+#include <u-boot/schedule.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include "nbx_imagetag.h"
+#include "nbx_nrboot.h"
+
+/* Partition offsets defined in Kconfig (CONFIG_NBX_MMC_PART_*) */
+
+/* Image Tag Functions */
+
+static int mvebu_imagetag_check(struct mvebu_image_tag *tag,
+				unsigned long maxsize, const char *name)
+{
+	if (be32_to_cpu(tag->magic) != MVEBU_IMAGE_TAG_MAGIC) {
+		if (name)
+			printf("%s: invalid TAG magic: %.8x\n", name,
+			       be32_to_cpu(tag->magic));
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->version) != MVEBU_IMAGE_TAG_VERSION) {
+		if (name)
+			printf("%s: invalid TAG version: %.8x\n", name,
+			       be32_to_cpu(tag->version));
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->total_size) < sizeof(*tag)) {
+		if (name)
+			printf("%s: tag size is too small!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->total_size) > maxsize) {
+		if (name)
+			printf("%s: tag size is too big!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->device_tree_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->device_tree_offset) +
+	    be32_to_cpu(tag->device_tree_size) > maxsize) {
+		if (name)
+			printf("%s: bogus device tree offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->kernel_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->kernel_offset) +
+	    be32_to_cpu(tag->kernel_size) > maxsize) {
+		if (name)
+			printf("%s: bogus kernel offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (be32_to_cpu(tag->rootfs_offset) < sizeof(*tag) ||
+	    be32_to_cpu(tag->rootfs_offset) +
+	    be32_to_cpu(tag->rootfs_size) > maxsize) {
+		if (name)
+			printf("%s: bogus rootfs offset/size!\n", name);
+		return -EINVAL;
+	}
+
+	if (name) {
+		/*
+		 * Ensure null-termination within the 32-byte fields
+		 * before printing to avoid displaying garbage.
+		 */
+		tag->image_name[sizeof(tag->image_name) - 1] = '\0';
+		tag->build_date[sizeof(tag->build_date) - 1] = '\0';
+		tag->build_user[sizeof(tag->build_user) - 1] = '\0';
+
+		printf("%s: Found valid tag: %s / %s / %s\n", name,
+		       tag->image_name, tag->build_date, tag->build_user);
+	}
+
+	return 0;
+}
+
+static int mvebu_imagetag_crc(struct mvebu_image_tag *tag, const char *name)
+{
+	u32 crc = ~0;
+
+	crc = crc32(crc, ((unsigned char *)tag) + 4,
+		    be32_to_cpu(tag->total_size) - 4);
+
+	if (be32_to_cpu(tag->crc) != crc) {
+		if (name)
+			printf("%s: invalid tag CRC!\n", name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* NRBoot (Reboot Tracking) Functions */
+
+struct mvebu_nrboot {
+	u16 nrboot;
+	u16 nrsuccess;
+};
+
+#define MVEBU_MAX_FAILURE	4
+
+static int mvebu_count_bits(u16 val)
+{
+	int i, found = 0;
+
+	for (i = 0; i < 16; i++) {
+		if (val & (1 << i))
+			found++;
+	}
+	return found;
+}
+
+int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset)
+{
+	struct blk_desc *bd = mmc_get_blk_desc(mmc);
+	struct mvebu_nrboot *nr;
+	uint blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	uint blk_cnt = ALIGN(sizeof(*nr), bd->blksz) / bd->blksz;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, blk_cnt * bd->blksz);
+	nr = (void *)buf;
+
+	n = blk_dread(bd, blk_start, blk_cnt, buf);
+	if (n != blk_cnt)
+		return 0;
+
+	printf(" - nr.nrboot = %04x\n", nr->nrboot);
+	printf(" - nr.nrsuccess = %04x\n", nr->nrsuccess);
+
+	/* Sanity check on values */
+	if (mvebu_count_bits(~nr->nrboot + 1) <= 1 &&
+	    mvebu_count_bits(~nr->nrsuccess + 1) <= 1) {
+		int boot, success;
+
+		boot = 16 - mvebu_count_bits(nr->nrboot);
+		success = 16 - mvebu_count_bits(nr->nrsuccess);
+
+		printf(" - Nrboot: %d / Nrsuccess: %d\n", boot, success);
+
+		if (boot == 16 || boot < success ||
+		    boot - success >= MVEBU_MAX_FAILURE) {
+			printf(" - Nrboot exceeded\n");
+			return 0;
+		}
+
+		/* Increment boot attempt counter */
+		boot++;
+		nr->nrboot = ~((1 << boot) - 1);
+
+		printf(" - Setting Nrboot to %d\n", boot);
+
+		n = blk_dwrite(bd, blk_start, blk_cnt, buf);
+		if (n != blk_cnt)
+			return 0;
+
+		return 1;
+	}
+
+	printf(" - Invalid NR values\n");
+
+	return 0;
+}
+
+/* emmcboot Command */
+
+static void mvebu_try_emmcboot(struct mmc *mmc, unsigned long offset,
+			       unsigned long maxsize, const char *bank)
+{
+	struct blk_desc *bd = mmc_get_blk_desc(mmc);
+	struct mvebu_image_tag *tag;
+	ulong image_addr = 0;
+	ulong fdt_addr = 0;
+	ulong tag_addr;
+	uint tag_blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	uint tag_blk_cnt = ALIGN(sizeof(*tag), bd->blksz) / bd->blksz;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, tag_buf, tag_blk_cnt * bd->blksz);
+	tag = (void *)tag_buf;
+
+	schedule();
+
+	printf("## Trying %s boot...\n", bank);
+
+	/* Load tag header */
+	n = blk_dread(bd, tag_blk_start, tag_blk_cnt, tag_buf);
+	if (n != tag_blk_cnt) {
+		printf("%s: failed to read tag header\n", bank);
+		return;
+	}
+
+	if (mvebu_imagetag_check(tag, maxsize, bank) != 0)
+		return;
+
+	if (tag->rootfs_size != 0) {
+		printf("%s: rootfs in tag not supported\n", bank);
+		return;
+	}
+
+	/* Get image and device tree load addresses from environment */
+	image_addr = env_get_ulong("image_addr", 16, 0);
+	if (!image_addr) {
+		puts("emmcboot needs image_addr\n");
+		return;
+	}
+
+	fdt_addr = env_get_ulong("fdt_addr", 16, 0);
+	if (!fdt_addr) {
+		puts("emmcboot needs fdt_addr\n");
+		return;
+	}
+
+	tag_addr = image_addr;
+
+	/* Load full image, temporarily reuse image_addr for this */
+	{
+		uint data_blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+		uint data_blk_cnt = ALIGN(mvebu_imagetag_total_size(tag),
+					  bd->blksz) / bd->blksz;
+
+		n = blk_dread(bd, data_blk_start, data_blk_cnt, (void *)tag_addr);
+		if (n != data_blk_cnt) {
+			printf("%s: failed to read full image\n", bank);
+			return;
+		}
+
+		if (mvebu_imagetag_crc((void *)tag_addr, bank) != 0)
+			return;
+	}
+
+	schedule();
+
+	/* Copy image and device tree to the right addresses */
+	/* We assume that image_addr + tag_size < fdt_addr */
+	{
+		tag = (void *)tag_addr;
+		memcpy((void *)fdt_addr,
+		       ((void *)tag_addr) + mvebu_imagetag_device_tree_offset(tag),
+		       mvebu_imagetag_device_tree_size(tag));
+		memmove((void *)image_addr,
+			((void *)tag_addr) + mvebu_imagetag_kernel_offset(tag),
+			mvebu_imagetag_kernel_size(tag));
+	}
+
+	schedule();
+
+	/* Set bootargs and boot */
+	{
+		char bootargs[256];
+		char *console_env;
+
+		console_env = env_get("console");
+		if (console_env)
+			snprintf(bootargs, sizeof(bootargs), "%s bank=%s",
+				 console_env, bank);
+		else
+			snprintf(bootargs, sizeof(bootargs), "bank=%s", bank);
+
+		env_set("bootargs", bootargs);
+
+		printf("## Booting kernel from %s...\n", bank);
+		printf("   Image addr: 0x%lx\n", image_addr);
+		printf("   FDT addr:   0x%lx\n", fdt_addr);
+
+		/* Build and run booti command */
+		{
+			char cmd[128];
+
+			snprintf(cmd, sizeof(cmd), "booti 0x%lx - 0x%lx",
+				 image_addr, fdt_addr);
+			run_command(cmd, 0);
+		}
+	}
+
+	printf("## %s boot failed\n", bank);
+}
+
+static int do_emmcboot(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	int dev;
+	struct mmc *mmc;
+
+	dev = 0;
+	if (argc >= 2)
+		dev = dectoul(argv[1], NULL);
+
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		printf("No MMC device %d found\n", dev);
+		return CMD_RET_FAILURE;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* Switch to partition 0 (user data area) */
+	if (blk_select_hwpart_devnum(UCLASS_MMC, dev, 0)) {
+		puts("MMC partition switch failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (mvebu_check_nrboot(mmc, CONFIG_NBX_MMC_PART_NRBOOT_OFFSET)) {
+		/* System is healthy: try newer bank first */
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1");
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0");
+	} else {
+		/* System is degraded: use stable bank first */
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0");
+		mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET,
+				   CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1");
+	}
+
+	puts("emmcboot: all boot attempts failed\n");
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+	emmcboot, 2, 0, do_emmcboot,
+	"boot from MVEBU eMMC image banks",
+	"[dev]\n"
+	"    - Boot from eMMC device <dev> (default 0)\n"
+	"    - Requires image_addr and fdt_addr environment variables\n"
+	"    - Uses dual-bank boot with automatic fallback\n"
+	"    - Bank selection based on reboot tracking (nrboot)"
+);
diff --git a/board/freebox/nbx10g/nbx_fbxserial.c b/board/freebox/nbx10g/nbx_fbxserial.c
new file mode 100644
index 00000000000..088133a9496
--- /dev/null
+++ b/board/freebox/nbx10g/nbx_fbxserial.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NBX Freebox Serial Info Support
+ *
+ * Copyright (C) 2025 Free Mobile, Freebox
+ *
+ * Reads device serial number and MAC address from eMMC.
+ * The serial info is stored at a fixed offset in the eMMC user area.
+ *
+ * Serial format: TTTT-VV-M-(YY)WW-NN-NNNNN / FLAGS
+ * Where:
+ *   TTTT  = Device type (e.g., 9018)
+ *   VV    = Board version
+ *   M     = Manufacturer code (ASCII)
+ *   YY    = Year (BCD)
+ *   WW    = Week (1-53)
+ *   NNNNN = Serial number
+ *   FLAGS = Feature flags
+ */
+
+#include <command.h>
+#include <dm/device.h>
+#include <env.h>
+#include <event.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <vsprintf.h>
+#include <u-boot/crc.h>
+#include <asm/byteorder.h>
+#include <linux/ctype.h>
+#include <linux/errno.h>
+#include "nbx_fbxserial.h"
+
+/* Partition offset defined in Kconfig (CONFIG_NBX_MMC_PART_SERIAL_OFFSET) */
+
+/*
+ * Validate serial info structure
+ */
+static int nbx_fbx_check_serial(struct nbx_fbx_serial *fs)
+{
+	unsigned int sum, len;
+
+	/* Check magic first */
+	if (be32_to_cpu(fs->magic) != NBX_FBXSERIAL_MAGIC) {
+		printf("Invalid magic for serial info (%08x != %08x)!\n",
+		       be32_to_cpu(fs->magic), NBX_FBXSERIAL_MAGIC);
+		return -EINVAL;
+	}
+
+	/* Check struct version */
+	if (be32_to_cpu(fs->struct_version) > NBX_FBXSERIAL_VERSION) {
+		printf("Version too big for fbxserial info (0x%08x)!\n",
+		       be32_to_cpu(fs->struct_version));
+		return -EINVAL;
+	}
+
+	/* Check for silly len */
+	len = be32_to_cpu(fs->len);
+	if (len > NBX_FBXSERIAL_MAX_SIZE) {
+		printf("Silly len for serial info (%d)\n", len);
+		return -EINVAL;
+	}
+
+	/* Validate CRC (crc32_no_comp: no one's complement) */
+	sum = crc32_no_comp(0, (void *)fs + 4, len - 4);
+	if (be32_to_cpu(fs->crc32) != sum) {
+		printf("Invalid checksum for serial info (%08x != %08x)\n",
+		       sum, be32_to_cpu(fs->crc32));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int nbx_fbx_read_serial(int dev_num, unsigned long offset,
+			struct nbx_fbx_serial *fs)
+{
+	struct mmc *mmc;
+	struct blk_desc *bd;
+	uint blk_start, blk_cnt;
+	uint n;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, ALIGN(sizeof(*fs), 512));
+	mmc = find_mmc_device(dev_num);
+	if (!mmc) {
+		printf("No MMC device %d found\n", dev_num);
+		nbx_fbxserial_set_default(fs);
+		return -ENODEV;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	/* Switch to partition 0 (user data area) */
+	if (blk_select_hwpart_devnum(UCLASS_MMC, dev_num, 0)) {
+		puts("MMC partition switch failed\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	bd = mmc_get_blk_desc(mmc);
+	if (!bd) {
+		puts("Failed to get MMC block descriptor\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	blk_start = ALIGN(offset, bd->blksz) / bd->blksz;
+	blk_cnt = ALIGN(sizeof(*fs), bd->blksz) / bd->blksz;
+
+	memset(fs, 0x42, sizeof(*fs));
+
+	n = blk_dread(bd, blk_start, blk_cnt, buf);
+	if (n != blk_cnt) {
+		printf("Failed to read serial info from MMC\n");
+		nbx_fbxserial_set_default(fs);
+		return -EIO;
+	}
+
+	memcpy(fs, buf, sizeof(*fs));
+
+	if (nbx_fbx_check_serial(fs) != 0) {
+		nbx_fbxserial_set_default(fs);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs)
+{
+	int i;
+
+	printf("Serial: %04u-%02u-%c-(%02u)%02u-%02u-%05u / %08x\n",
+	       ntohs(fs->type),
+	       fs->version,
+	       isprint(fs->manufacturer) ? fs->manufacturer : '?',
+	       ntohs(fs->year) / 100,
+	       ntohs(fs->year) % 100,
+	       fs->week,
+	       ntohl(fs->number),
+	       ntohl(fs->flags));
+
+	printf("Mac:    %02X:%02X:%02X:%02X:%02X:%02X\n",
+	       fs->mac_addr_base[0],
+	       fs->mac_addr_base[1],
+	       fs->mac_addr_base[2],
+	       fs->mac_addr_base[3],
+	       fs->mac_addr_base[4],
+	       fs->mac_addr_base[5]);
+
+	/* Show bundle info */
+	for (i = 0; i < be32_to_cpu(fs->extinfo_count); i++) {
+		struct nbx_serial_extinfo *p;
+
+		if (i >= NBX_EXTINFO_MAX_COUNT)
+			break;
+
+		p = &fs->extinfos[i];
+		if (be32_to_cpu(p->type) == NBX_EXTINFO_TYPE_EXTDEV &&
+		    be32_to_cpu(p->u.extdev.type) == NBX_EXTDEV_TYPE_BUNDLE) {
+			/* Ensure null termination */
+			p->u.extdev.serial[sizeof(p->u.extdev.serial) - 1] = 0;
+			printf("Bundle: %s\n", p->u.extdev.serial);
+		}
+	}
+
+	printf("\n");
+}
+
+int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset)
+{
+	struct nbx_fbx_serial fs;
+	char mac[32];
+	int ret;
+
+	ret = nbx_fbx_read_serial(dev_num, offset, &fs);
+
+	/* Even on error, fs has default values set */
+	snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x",
+		 fs.mac_addr_base[0], fs.mac_addr_base[1],
+		 fs.mac_addr_base[2], fs.mac_addr_base[3],
+		 fs.mac_addr_base[4], fs.mac_addr_base[5]);
+
+	nbx_fbx_dump_serial(&fs);
+
+	env_set("ethaddr", mac);
+	env_set("eth1addr", mac);
+	env_set("eth2addr", mac);
+
+	return ret;
+}
+
+/*
+ * fbxserial show - display serial info from eMMC
+ */
+static int do_fbxserial_show(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	struct nbx_fbx_serial fs;
+	int dev = 0;
+	unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET;
+
+	if (argc >= 1)
+		dev = dectoul(argv[0], NULL);
+
+	if (argc >= 2)
+		offset = hextoul(argv[1], NULL);
+
+	if (nbx_fbx_read_serial(dev, offset, &fs) != 0)
+		printf("Warning: Using default serial info\n");
+
+	nbx_fbx_dump_serial(&fs);
+
+	return CMD_RET_SUCCESS;
+}
+
+/*
+ * fbxserial init - initialize ethaddr from serial info
+ */
+static int do_fbxserial_init(struct cmd_tbl *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	int dev = 0;
+	unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET;
+
+	if (argc >= 1)
+		dev = dectoul(argv[0], NULL);
+
+	if (argc >= 2)
+		offset = hextoul(argv[1], NULL);
+
+	return nbx_fbx_init_ethaddr(dev, offset);
+}
+
+static struct cmd_tbl cmd_fbxserial_sub[] = {
+	U_BOOT_CMD_MKENT(show, 3, 0, do_fbxserial_show, "", ""),
+	U_BOOT_CMD_MKENT(init, 3, 0, do_fbxserial_init, "", ""),
+};
+
+static int do_fbxserial(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct cmd_tbl *cp;
+
+	/* Default to 'show' if no subcommand */
+	if (argc < 2)
+		return do_fbxserial_show(cmdtp, flag, 0, NULL);
+
+	cp = find_cmd_tbl(argv[1], cmd_fbxserial_sub,
+			  ARRAY_SIZE(cmd_fbxserial_sub));
+
+	if (!cp)
+		return CMD_RET_USAGE;
+
+	return cp->cmd(cmdtp, flag, argc - 2, argv + 2);
+}
+
+U_BOOT_CMD(
+	fbxserial, 5, 0, do_fbxserial,
+	"NBX serial info and MAC address initialization",
+	"show [dev] [offset] - display serial info from eMMC\n"
+	"fbxserial init [dev] [offset] - initialize ethaddr from serial info\n"
+	"    dev    - MMC device number (default 0)\n"
+	"    offset - offset in eMMC in hex (default from Kconfig)"
+);
+
+/*
+ * Early init hook: Set MAC address from eMMC serial info before
+ * network driver probes. EVT_SETTINGS_R is triggered after MMC
+ * is available but before initr_net().
+ */
+static int nbx_fbx_settings_r(void)
+{
+	if (!of_machine_is_compatible("nbx,armada8040"))
+		return 0;
+
+	nbx_fbx_init_ethaddr(0, CONFIG_NBX_MMC_PART_SERIAL_OFFSET);
+	return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_SETTINGS_R, nbx_fbx_settings_r);
diff --git a/board/freebox/nbx10g/nbx_fbxserial.h b/board/freebox/nbx10g/nbx_fbxserial.h
new file mode 100644
index 00000000000..7bcaef09fe3
--- /dev/null
+++ b/board/freebox/nbx10g/nbx_fbxserial.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NBX Freebox Serial Info Support
+ *
+ * Copyright (C) 2025 Free Mobile, Freebox
+ *
+ * Reads device serial number and MAC address from eMMC.
+ * Used to identify the board and set network MAC addresses.
+ */
+
+#ifndef NBX_FBXSERIAL_H
+#define NBX_FBXSERIAL_H
+
+#include <linux/types.h>
+
+/*
+ * Extended info structure - variable data depending on type
+ */
+#define NBX_EXTINFO_SIZE		128
+#define NBX_EXTINFO_MAX_COUNT		16
+
+/* Extended info types */
+#define NBX_EXTINFO_TYPE_EXTDEV		1
+
+/* Extended device types */
+#define NBX_EXTDEV_TYPE_BUNDLE		1
+#define NBX_EXTDEV_TYPE_MAX		2
+
+struct nbx_serial_extinfo {
+	u32 type;
+
+	union {
+		/* extdev */
+		struct {
+			u32 type;
+			u32 model;
+			char serial[64];
+		} extdev;
+
+		/* raw access */
+		unsigned char data[NBX_EXTINFO_SIZE];
+	} u;
+} __packed;
+
+/*
+ * Master serial structure
+ */
+#define NBX_FBXSERIAL_VERSION		1
+#define NBX_FBXSERIAL_MAGIC		0x2d9521ab
+
+#define NBX_MAC_ADDR_SIZE		6
+#define NBX_RANDOM_DATA_SIZE		32
+
+/* Maximum size for CRC validation */
+#define NBX_FBXSERIAL_MAX_SIZE		8192
+
+struct nbx_fbx_serial {
+	u32 crc32;
+	u32 magic;
+	u32 struct_version;
+	u32 len;
+
+	/* Board serial */
+	u16 type;
+	u8 version;
+	u8 manufacturer;
+	u16 year;
+	u8 week;
+	u32 number;
+	u32 flags;
+
+	/* MAC address base */
+	u8 mac_addr_base[NBX_MAC_ADDR_SIZE];
+
+	/* MAC address count */
+	u8 mac_count;
+
+	/* Random data used to derive keys */
+	u8 random_data[NBX_RANDOM_DATA_SIZE];
+
+	/* Last update of data (seconds since epoch) */
+	u32 last_modified;
+
+	/* Count of following extinfo tags */
+	u32 extinfo_count;
+
+	/* Beginning of extended info */
+	struct nbx_serial_extinfo extinfos[NBX_EXTINFO_MAX_COUNT];
+} __packed;
+
+/**
+ * nbx_fbxserial_set_default() - Initialize serial structure with defaults
+ * @serial: Pointer to serial structure to initialize
+ *
+ * Sets the serial structure to default values (Freebox OUI, type 9018).
+ * Used as fallback when serial info cannot be read from eMMC.
+ */
+static inline void nbx_fbxserial_set_default(struct nbx_fbx_serial *serial)
+{
+	static const struct nbx_fbx_serial def = {
+		.crc32		= 0,
+		.magic		= NBX_FBXSERIAL_MAGIC,
+		.struct_version	= NBX_FBXSERIAL_VERSION,
+		.len		= sizeof(struct nbx_fbx_serial),
+		.type		= 9018,
+		.version	= 0,
+		.manufacturer	= '_',
+		.year		= 0,
+		.week		= 0,
+		.number		= 0,
+		.flags		= 0,
+		.mac_addr_base	= { 0x00, 0x07, 0xCB, 0x00, 0x00, 0xFD },
+		.mac_count	= 1,
+		.random_data	= { 0 },
+		.last_modified	= 0,
+		.extinfo_count	= 0,
+	};
+
+	memcpy(serial, &def, sizeof(def));
+}
+
+/**
+ * nbx_fbx_read_serial() - Read serial info from eMMC
+ * @dev_num: MMC device number
+ * @offset: Byte offset in eMMC where serial info is stored
+ * @fs: Pointer to serial structure to fill
+ *
+ * Reads and validates the serial info from eMMC. On failure,
+ * the structure is filled with default values.
+ *
+ * Return: 0 on success, negative on error (defaults still set)
+ */
+int nbx_fbx_read_serial(int dev_num, unsigned long offset,
+			struct nbx_fbx_serial *fs);
+
+/**
+ * nbx_fbx_dump_serial() - Print serial info to console
+ * @fs: Pointer to serial structure to display
+ *
+ * Prints the serial number, MAC address, and bundle info (if present).
+ */
+void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs);
+
+/**
+ * nbx_fbx_init_ethaddr() - Initialize Ethernet addresses from serial info
+ * @dev_num: MMC device number
+ * @offset: Byte offset in eMMC where serial info is stored
+ *
+ * Reads serial info and sets ethaddr, eth1addr, eth2addr environment
+ * variables from the MAC address in the serial structure.
+ *
+ * Return: 0 on success, negative on error
+ */
+int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset);
+
+#endif /* NBX_FBXSERIAL_H */
diff --git a/board/freebox/nbx10g/nbx_imagetag.h b/board/freebox/nbx10g/nbx_imagetag.h
new file mode 100644
index 00000000000..999293dd58a
--- /dev/null
+++ b/board/freebox/nbx10g/nbx_imagetag.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MVEBU Image Tag header
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ */
+
+#ifndef __MVEBU_IMAGETAG_H
+#define __MVEBU_IMAGETAG_H
+
+#include <linux/types.h>
+
+#define MVEBU_IMAGE_TAG_MAGIC	0x8d7c90bc
+#define MVEBU_IMAGE_TAG_VERSION	1
+
+/**
+ * struct mvebu_image_tag - MVEBU boot image tag structure
+ *
+ * All multi-byte fields are stored in big-endian format.
+ */
+struct mvebu_image_tag {
+	u32 crc;			/* CRC32-LE checksum (from offset 4) */
+	u32 magic;			/* Magic: 0x8d7c90bc */
+	u32 version;			/* Version: 1 */
+	u32 total_size;			/* Total image size including tag */
+	u32 flags;			/* Feature flags (reserved) */
+
+	u32 device_tree_offset;		/* Offset from tag start to DTB */
+	u32 device_tree_size;		/* DTB size in bytes */
+
+	u32 kernel_offset;		/* Offset from tag start to kernel */
+	u32 kernel_size;		/* Kernel size in bytes */
+
+	u32 rootfs_offset;		/* Offset from tag start to rootfs */
+	u32 rootfs_size;		/* Rootfs size (must be 0) */
+
+	char image_name[32];		/* Image name (null-terminated) */
+	char build_user[32];		/* Build user info */
+	char build_date[32];		/* Build date info */
+};
+
+/* Accessor functions for big-endian fields */
+static inline u32 mvebu_imagetag_device_tree_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->device_tree_offset);
+}
+
+static inline u32 mvebu_imagetag_device_tree_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->device_tree_size);
+}
+
+static inline u32 mvebu_imagetag_kernel_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->kernel_offset);
+}
+
+static inline u32 mvebu_imagetag_kernel_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->kernel_size);
+}
+
+static inline u32 mvebu_imagetag_rootfs_offset(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->rootfs_offset);
+}
+
+static inline u32 mvebu_imagetag_rootfs_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->rootfs_size);
+}
+
+static inline u32 mvebu_imagetag_total_size(struct mvebu_image_tag *tag)
+{
+	return be32_to_cpu(tag->total_size);
+}
+
+#endif /* __MVEBU_IMAGETAG_H */
diff --git a/board/freebox/nbx10g/nbx_nrboot.h b/board/freebox/nbx10g/nbx_nrboot.h
new file mode 100644
index 00000000000..91c9fb2e57b
--- /dev/null
+++ b/board/freebox/nbx10g/nbx_nrboot.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MVEBU NRBoot (Number of Reboots) tracking header
+ *
+ * Copyright (C) 2026 Free Mobile, Freebox
+ */
+
+#ifndef __MVEBU_NRBOOT_H
+#define __MVEBU_NRBOOT_H
+
+#include <mmc.h>
+
+/**
+ * mvebu_check_nrboot() - Check and update reboot tracking counter
+ * @mmc: MMC device
+ * @offset: Byte offset in MMC where nrboot data is stored
+ *
+ * This function reads the reboot tracking counter, checks if we've
+ * exceeded the maximum number of failed boots (4), and updates the
+ * counter for the current boot attempt.
+ *
+ * The counter uses a bit-field encoding:
+ * - nrboot: Running count of boot attempts
+ * - nrsuccess: Count of successful boots
+ *
+ * If boot - success >= MAX_FAILURE (4), the system is considered
+ * degraded and should use the fallback boot bank.
+ *
+ * Return: 1 if system is healthy (try newer bank first),
+ *         0 if system is degraded (use stable bank first)
+ */
+int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset);
+
+#endif /* __MVEBU_NRBOOT_H */
diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c
index eb10cd5143d..5e560a7f927 100644
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c
@@ -532,17 +532,17 @@ int dram_init_banksize(void)
 	/* set global data memory */
 	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size  = CFG_SYS_SDRAM_SIZE;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size  = CFG_SYS_SDRAM_SIZE;
 
 	/* Number of Row: 14 bits */
 	if ((reg_val >> 28) == 14)
-		gd->bd->bi_dram[0].size -= 0x20000000;
+		gd->dram[0].size -= 0x20000000;
 
 	/* Number of Memory Chips */
 	if ((reg_val & 0x3) > 1) {
-		gd->bd->bi_dram[1].start = 0x80000000;
-		gd->bd->bi_dram[1].size  = 0x40000000;
+		gd->dram[1].start = 0x80000000;
+		gd->dram[1].size  = 0x40000000;
 	}
 	return 0;
 }
diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c
index ddb7304d493..f7751fd6fb1 100644
--- a/board/ge/b1x5v2/b1x5v2.c
+++ b/board/ge/b1x5v2/b1x5v2.c
@@ -320,7 +320,7 @@ int overwrite_console(void)
 
 int board_early_init_f(void)
 {
-	select_ldb_di_clock_source(MXC_PLL5_CLK);
+	select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
 
 	return 0;
 }
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index e1d08475e94..9fc5f604a49 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -383,7 +383,7 @@ int board_early_init_f(void)
 
 #if defined(CONFIG_VIDEO_IPUV3)
 	/* Set LDB clock to Video PLL */
-	select_ldb_di_clock_source(MXC_PLL5_CLK);
+	select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
 #endif
 	return 0;
 }
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index cb9b88a1a58..d3a385bf6b7 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -71,11 +71,11 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = mx53_dram_size[0];
 
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size = mx53_dram_size[1];
 
 	return 0;
 }
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index b4053fa097d..2bb54d59bb8 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -293,7 +293,7 @@ static int coral_write_acpi_tables(const struct udevice *dev,
 	return 0;
 }
 
-struct acpi_ops coral_acpi_ops = {
+static const struct acpi_ops __maybe_unused coral_acpi_ops = {
 	.write_tables	= coral_write_acpi_tables,
 	.inject_dsdt	= chromeos_acpi_gpio_generate,
 };
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 5e60ab9d7b7..ba0465cf96f 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -456,23 +456,23 @@ int dram_init_banksize(void)
 	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
 	*/
 
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = 0x05e00000;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = 0x05e00000;
 
-	gd->bd->bi_dram[1].start = 0x05f00000;
-	gd->bd->bi_dram[1].size = 0x00001000;
+	gd->dram[1].start = 0x05f00000;
+	gd->dram[1].size = 0x00001000;
 
-	gd->bd->bi_dram[2].start = 0x05f02000;
-	gd->bd->bi_dram[2].size = 0x00efd000;
+	gd->dram[2].start = 0x05f02000;
+	gd->dram[2].size = 0x00efd000;
 
-	gd->bd->bi_dram[3].start = 0x06e00000;
-	gd->bd->bi_dram[3].size = 0x0060f000;
+	gd->dram[3].start = 0x06e00000;
+	gd->dram[3].size = 0x0060f000;
 
-	gd->bd->bi_dram[4].start = 0x07410000;
-	gd->bd->bi_dram[4].size = 0x1aaf0000;
+	gd->dram[4].start = 0x07410000;
+	gd->dram[4].size = 0x1aaf0000;
 
-	gd->bd->bi_dram[5].start = 0x22000000;
-	gd->bd->bi_dram[5].size = 0x1c000000;
+	gd->dram[5].start = 0x22000000;
+	gd->dram[5].size = 0x1c000000;
 
 	return 0;
 }
diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c
index fb56762fff6..e7908d4c048 100644
--- a/board/hisilicon/hikey960/hikey960.c
+++ b/board/hisilicon/hikey960/hikey960.c
@@ -74,8 +74,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c
index c3ea080ff75..dbab67d6f65 100644
--- a/board/hisilicon/poplar/poplar.c
+++ b/board/hisilicon/poplar/poplar.c
@@ -87,8 +87,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
-	gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
+	gd->dram[0].start = KERNEL_TEXT_OFFSET;
+	gd->dram[0].size = gd->ram_size - gd->dram[0].start;
 
 	return 0;
 }
diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
index 965847d9650..d7d8bfd0a76 100644
--- a/board/imgtec/boston/Kconfig
+++ b/board/imgtec/boston/Kconfig
@@ -11,7 +11,7 @@ config SYS_CONFIG_NAME
 
 
 config ENV_SOURCE_FILE
-       default "boston"
+	default "boston"
 
 config TEXT_BASE
 	default 0x9fc00000 if 32BIT
diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index efb7b49cbe0..07668bae7a9 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -39,8 +39,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c
index 51938a1b4d8..e37d4e767db 100644
--- a/board/keymile/pg-wcom-ls102xa/ddr.c
+++ b/board/keymile/pg-wcom-ls102xa/ddr.c
@@ -84,8 +84,8 @@ int fsl_initdram(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/board/kontron/pitx_imx8m/MAINTAINERS b/board/kontron/pitx_imx8m/MAINTAINERS
index aad84528e33..8c43526691b 100644
--- a/board/kontron/pitx_imx8m/MAINTAINERS
+++ b/board/kontron/pitx_imx8m/MAINTAINERS
@@ -1,7 +1,6 @@
 Kontron pITX-imx8m Board
 M:	Heiko Thiery <heiko.thiery@gmail.com>
 S:	Maintained
-F:	arch/arm/dts/imx8mq-kontron-pitx-imx8m*
 F:	board/kontron/pitx_imx8m/*
 F:	include/configs/kontron_pitx_imx8m.h
 F:	configs/kontron_pitx_imx8m_defconfig
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 8a9502037fb..ce778bc0849 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	/* fixup DT for the two GPP DDR banks */
 	for (i = 0; i < nbanks; i++) {
-		base[i] = gd->bd->bi_dram[i].start;
-		size[i] = gd->bd->bi_dram[i].size;
+		base[i] = gd->dram[i].start;
+		size[i] = gd->dram[i].size;
 	}
 
 	fdt_fixup_memory_banks(blob, base, size, nbanks);
diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c
index 0710316a48b..cc741dea504 100644
--- a/board/kontron/sl28/spl_atf.c
+++ b/board/kontron/sl28/spl_atf.c
@@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
 
 	dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
-		dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
-		dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
+		dram_regions_info.region[i].addr = gd->dram[i].start;
+		dram_regions_info.region[i].size = gd->dram[i].size;
+		dram_regions_info.total_dram_size += gd->dram[i].size;
 	}
 
 	bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c
index e1ff041c54f..ba922b43064 100644
--- a/board/liebherr/btt/btt.c
+++ b/board/liebherr/btt/btt.c
@@ -239,7 +239,7 @@ int spl_start_uboot(void)
 
 static const char *get_board_name(void)
 {
-	if (gd->bd->bi_dram[0].size == SZ_128M)
+	if (gd->dram[0].size == SZ_128M)
 		return STR_BTTC;
 
 	return STR_BTT3;
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
index f5e2f58b12b..dfc196124f3 100644
--- a/board/logicpd/imx6/Kconfig
+++ b/board/logicpd/imx6/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
        default "imx6"
 
 config SYS_VENDOR
-       default "logicpd"
+	default "logicpd"
 
 config SYS_CONFIG_NAME
        default "imx6_logic"
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index fc76d5765fa..5e76942783f 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -69,11 +69,11 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = mx53_dram_size[0];
 
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size = mx53_dram_size[1];
 
 	return 0;
 }
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index 05c4dd187fe..68d516c7db8 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -57,7 +57,7 @@ int dram_init_banksize(void)
 {
 	phys_size_t ram_size = gd->ram_size;
 
-	gd->bd->bi_dram[0].start = 0;
+	gd->dram[0].start = 0;
 
 	#if defined(CONFIG_SYS_MEM_TOP_HIDE)
 		ram_size += CONFIG_SYS_MEM_TOP_HIDE;
@@ -69,25 +69,25 @@ int dram_init_banksize(void)
 	case DRAM_1GB_SIZE:
 	case DRAM_2GB_ECC_SIZE:
 	case DRAM_2GB_SIZE:
-		gd->bd->bi_dram[0].size = ram_size;
-		gd->bd->bi_dram[1].start = 0;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[0].size = ram_size;
+		gd->dram[1].start = 0;
+		gd->dram[1].size = 0;
 		break;
 	case DRAM_4GB_ECC_SIZE:
-		gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
-		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
-		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
+		gd->dram[0].size = DRAM_2GB_SIZE;
+		gd->dram[1].start = DRAM_4GB_SIZE;
+		gd->dram[1].size = DRAM_2GB_SIZE -
 			(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
 		break;
 	case DRAM_4GB_SIZE:
-		gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
-		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
-		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
+		gd->dram[0].size = DRAM_2GB_SIZE;
+		gd->dram[1].start = DRAM_4GB_SIZE;
+		gd->dram[1].size = DRAM_2GB_SIZE;
 		break;
 	default:
-		gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
-		gd->bd->bi_dram[1].start = 0;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[0].size = DRAM_1GB_SIZE;
+		gd->dram[1].start = 0;
+		gd->dram[1].size = 0;
 		break;
 	}
 
diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env
index d59bd6fd5ed..88eefaa35e5 100644
--- a/board/nxp/imx8mm_evk/imx8mm_evk.env
+++ b/board/nxp/imx8mm_evk/imx8mm_evk.env
@@ -12,6 +12,8 @@ initrd_addr=0x48080000
 image=Image
 ip_dyn=yes
 kernel_addr_r=0x42000000
+kernel_comp_addr_r=0x60000000
+kernel_comp_size=0x2000000
 loadaddr=CONFIG_SYS_LOAD_ADDR
 mmcautodetect=yes
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env
index cffa83bf792..fbdf202c573 100644
--- a/board/nxp/imx8mn_evk/imx8mn_evk.env
+++ b/board/nxp/imx8mn_evk/imx8mn_evk.env
@@ -12,6 +12,8 @@ initrd_addr=0x48080000
 image=Image
 ip_dyn=yes
 kernel_addr_r=0x42000000
+kernel_comp_addr_r=0x60000000
+kernel_comp_size=0x2000000
 loadaddr=CONFIG_SYS_LOAD_ADDR
 mmcautodetect=yes
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env
index e994b93b168..dfc922e6215 100644
--- a/board/nxp/imx8mp_evk/imx8mp_evk.env
+++ b/board/nxp/imx8mp_evk/imx8mp_evk.env
@@ -10,6 +10,8 @@ fdt_addr=0x43000000
 fdtfile=DEFAULT_FDT_FILE
 image=Image
 ip_dyn=yes
+kernel_comp_addr_r=0x80000000
+kernel_comp_size=0x2000000
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
 mmcpart=1
 mmcroot=/dev/mmcblk1p2 rootwait rw
diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c
index 27cd82e745a..cd7d79b382d 100644
--- a/board/nxp/imx8mp_evk/spl.c
+++ b/board/nxp/imx8mp_evk/spl.c
@@ -65,7 +65,7 @@ int power_init_board(void)
 	 * Enable DVS control through PMIC_STBY_REQ and
 	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
 	 */
-	if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
+	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
 		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 	else
 		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env
index 6575dd7cb07..dd674afac91 100644
--- a/board/nxp/imx8mq_evk/imx8mq_evk.env
+++ b/board/nxp/imx8mq_evk/imx8mq_evk.env
@@ -10,6 +10,8 @@ initrd_addr=0x43800000
 image=Image
 ip_dyn=yes
 kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0x80000000
+kernel_comp_size=0x2000000
 loadaddr=CONFIG_SYS_LOAD_ADDR
 mmcautodetect=yes
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env
index b2ed1901a2b..76fadc00eeb 100644
--- a/board/nxp/imx93_evk/imx93_evk.env
+++ b/board/nxp/imx93_evk/imx93_evk.env
@@ -10,13 +10,16 @@ fdt_addr_r=0x83000000
 fdt_addr=0x83000000
 fdtfile=DEFAULT_FDT_FILE
 image=Image
+ip_dyn=yes
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
 mmcpart=1
 mmcroot=/dev/mmcblk1p2 rootwait rw
 mmcautodetect=yes
 mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
 prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
-kernel_addr_r=CONFIG_SYS_LOAD_ADDR
 loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
 loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
 loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile
index 9612b1fa55b..751ebfc9458 100644
--- a/board/nxp/imx93_frdm/Makefile
+++ b/board/nxp/imx93_frdm/Makefile
@@ -7,5 +7,5 @@
 obj-y += imx93_frdm.o
 
 ifdef CONFIG_XPL_BUILD
-obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o
+obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o
 endif
diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env
index 9af3bdfd714..96096bc51a0 100644
--- a/board/nxp/imx93_frdm/imx93_frdm.env
+++ b/board/nxp/imx93_frdm/imx93_frdm.env
@@ -10,12 +10,15 @@ fdt_addr_r=0x83000000
 fdt_addr=0x83000000
 fdtfile=DEFAULT_FDT_FILE
 image=Image
+ip_dyn=yes
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 mmcdev=1
 mmcpart=1
 mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw
 mmcautodetect=yes
 mmcargs=setenv bootargs console=${console} root=${mmcroot}
-kernel_addr_r=CONFIG_SYS_LOAD_ADDR
 loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
 loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
 boot_os=booti ${loadaddr} - ${fdt_addr_r}
diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h
index 192bc9e1519..3ff50d8519b 100644
--- a/board/nxp/imx93_frdm/lpddr4_timing.h
+++ b/board/nxp/imx93_frdm/lpddr4_timing.h
@@ -7,6 +7,7 @@
 #define __LPDDR4_TIMING_H__
 
 extern struct dram_timing_info dram_timing_1GB;
-extern struct dram_timing_info dram_timing_2GB;
+extern struct dram_timing_info dram_timing_1CS_2GB;
+extern struct dram_timing_info dram_timing_2CS_2GB;
 
 #endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c
index cd129e12959..5439a039c3d 100644
--- a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c
+++ b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c
@@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 };
 
 /* ddr timing config params */
-struct dram_timing_info dram_timing_2GB = {
+struct dram_timing_info dram_timing_1CS_2GB = {
 	.ddrc_cfg = ddr_ddrc_cfg,
 	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
 	.ddrphy_cfg = ddr_ddrphy_cfg,
diff --git a/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c
new file mode 100644
index 00000000000..79539941412
--- /dev/null
+++ b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c
@@ -0,0 +1,2006 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ *
+ * Generated code from DDR Gear
+ *
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x4e300110, 0x44104001 },
+	{ 0x4e301000, 0x0 },
+	{ 0x4e300000, 0x8000ff },
+	{ 0x4e300008, 0x0 },
+	{ 0x4e300080, 0x80000412 },
+	{ 0x4e300084, 0x80000412 },
+	{ 0x4e300114, 0x1002 },
+	{ 0x4e300260, 0x80 },
+	{ 0x4e30017c, 0x0 },
+	{ 0x4e300f04, 0x80 },
+	{ 0x4e300800, 0x43b30002 },
+	{ 0x4e300804, 0x1f1f1f1f },
+	{ 0x4e301240, 0x0 },
+	{ 0x4e301244, 0x0 },
+	{ 0x4e301248, 0x0 },
+	{ 0x4e30124c, 0x0 },
+	{ 0x4e301250, 0x0 },
+	{ 0x4e301254, 0x0 },
+	{ 0x4e301258, 0x0 },
+	{ 0x4e30125c, 0x0 },
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+	{
+		{
+			{ 0x4e300100, 0x24a0321b },
+			{ 0x4e300104, 0xfaee001b },
+			{ 0x4e300108, 0x2f2e3233 },
+			{ 0x4e30010c, 0x5c18b },
+			{ 0x4e300124, 0x1c790000 },
+			{ 0x4e300160, 0x9102 },
+			{ 0x4e30016c, 0x35f00000 },
+			{ 0x4e300170, 0x8b0b0608 },
+			{ 0x4e300250, 0x28 },
+			{ 0x4e300254, 0xfe00fe },
+			{ 0x4e300258, 0x8 },
+			{ 0x4e30025c, 0x400 },
+			{ 0x4e300300, 0x224f2213 },
+			{ 0x4e300304, 0xfe2213 },
+			{ 0x4e300308, 0xa380e3c },
+		},
+		{
+			{ 0x01, 0xe4 },
+			{ 0x02, 0x36 },
+			{ 0x03, 0x32 },
+			{ 0x0b, 0x26 },
+			{ 0x0c, 0x11 },
+			{ 0x0e, 0x11 },
+			{ 0x16, 0x04 },
+		},
+		0,
+	},
+	{
+		{
+			{ 0x4e300100, 0x124f2100 },
+			{ 0x4e300104, 0xf877000e },
+			{ 0x4e300108, 0x1816e4aa },
+			{ 0x4e30010c, 0x5101e6 },
+			{ 0x4e300124, 0xe3c0000 },
+			{ 0x4e300160, 0x9102 },
+			{ 0x4e30016c, 0x30900000 },
+			{ 0x4e300170, 0x8a0a0508 },
+			{ 0x4e300250, 0x14 },
+			{ 0x4e300254, 0x7b007b },
+			{ 0x4e300258, 0x8 },
+			{ 0x4e30025c, 0x400 },
+		},
+		{
+			{ 0x01, 0xb4 },
+			{ 0x02, 0x1b },
+			{ 0x03, 0x32 },
+			{ 0x0b, 0x26 },
+			{ 0x0c, 0x11 },
+			{ 0x0e, 0x11 },
+			{ 0x16, 0x04 },
+		},
+		0,
+	},
+	{
+		{
+			{ 0x4e300100, 0x51000 },
+			{ 0x4e300104, 0xf855000a },
+			{ 0x4e300108, 0x6e620a48 },
+			{ 0x4e30010c, 0x31010d },
+			{ 0x4e300124, 0x4c50000 },
+			{ 0x4e300160, 0x9102 },
+			{ 0x4e30016c, 0x30000000 },
+			{ 0x4e300170, 0x89090408 },
+			{ 0x4e300250, 0x7 },
+			{ 0x4e300254, 0x240024 },
+			{ 0x4e300258, 0x8 },
+			{ 0x4e30025c, 0x400 },
+		},
+		{
+			{ 0x01, 0x94 },
+			{ 0x02, 0x09 },
+			{ 0x03, 0x32 },
+			{ 0x0b, 0x26 },
+			{ 0x0c, 0x11 },
+			{ 0x0e, 0x11 },
+			{ 0x16, 0x04 },
+		},
+		1,
+	},
+};
+
+/* Auto Generated by SNPS PHY Init code
+ * which inlcude PHYINIT, 1D/2D message block
+ * rerention CSR, PIE
+ */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+/* ADDR mapping is from ds file. */
+	{ 0x100a0, 0x4 },
+	{ 0x100a1, 0x5 },
+	{ 0x100a2, 0x6 },
+	{ 0x100a3, 0x7 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x1 },
+	{ 0x100a6, 0x2 },
+	{ 0x100a7, 0x3 },
+	{ 0x110a0, 0x3 },
+	{ 0x110a1, 0x2 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x1 },
+	{ 0x110a4, 0x7 },
+	{ 0x110a5, 0x6 },
+	{ 0x110a6, 0x4 },
+	{ 0x110a7, 0x5 },
+/* End of ADDR mapping. */
+	{ 0x1005f, 0x5ff},
+	{ 0x1015f, 0x5ff},
+	{ 0x1105f, 0x5ff},
+	{ 0x1115f, 0x5ff},
+	{ 0x11005f, 0x5ff},
+	{ 0x11015f, 0x5ff},
+	{ 0x11105f, 0x5ff},
+	{ 0x11115f, 0x5ff},
+	{ 0x21005f, 0x5ff},
+	{ 0x21015f, 0x5ff},
+	{ 0x21105f, 0x5ff},
+	{ 0x21115f, 0x5ff},
+	{ 0x55, 0x1ff},
+	{ 0x1055, 0x1ff},
+	{ 0x2055, 0x1ff},
+	{ 0x200c5, 0x19},
+	{ 0x1200c5, 0xb},
+	{ 0x2200c5, 0x7},
+	{ 0x2002e, 0x2},
+	{ 0x12002e, 0x2},
+	{ 0x22002e, 0x2},
+	{ 0x90204, 0x0},
+	{ 0x190204, 0x0},
+	{ 0x290204, 0x0},
+	{ 0x20024, 0x1e3},
+	{ 0x2003a, 0x2},
+	{ 0x2007d, 0x212},
+	{ 0x2007c, 0x61},
+	{ 0x120024, 0x1e3},
+	{ 0x2003a, 0x2},
+	{ 0x12007d, 0x212},
+	{ 0x12007c, 0x61},
+	{ 0x220024, 0x1e3},
+	{ 0x2003a, 0x2},
+	{ 0x22007d, 0x212},
+	{ 0x22007c, 0x61},
+	{ 0x20056, 0x3},
+	{ 0x120056, 0x3},
+	{ 0x220056, 0x3},
+	{ 0x1004d, 0x600},
+	{ 0x1014d, 0x600},
+	{ 0x1104d, 0x600},
+	{ 0x1114d, 0x600},
+	{ 0x11004d, 0x600},
+	{ 0x11014d, 0x600},
+	{ 0x11104d, 0x600},
+	{ 0x11114d, 0x600},
+	{ 0x21004d, 0x600},
+	{ 0x21014d, 0x600},
+	{ 0x21104d, 0x600},
+	{ 0x21114d, 0x600},
+	{ 0x10049, 0xe00},
+	{ 0x10149, 0xe00},
+	{ 0x11049, 0xe00},
+	{ 0x11149, 0xe00},
+	{ 0x110049, 0xe00},
+	{ 0x110149, 0xe00},
+	{ 0x111049, 0xe00},
+	{ 0x111149, 0xe00},
+	{ 0x210049, 0xe00},
+	{ 0x210149, 0xe00},
+	{ 0x211049, 0xe00},
+	{ 0x211149, 0xe00},
+	{ 0x43, 0x60},
+	{ 0x1043, 0x60},
+	{ 0x2043, 0x60},
+	{ 0x20018, 0x1},
+	{ 0x20075, 0x4},
+	{ 0x20050, 0x0},
+	{ 0x2009b, 0x2},
+	{ 0x20008, 0x3a5},
+	{ 0x120008, 0x1d3},
+	{ 0x220008, 0x9c},
+	{ 0x20088, 0x9},
+	{ 0x200b2, 0x10c},
+	{ 0x10043, 0x5a1},
+	{ 0x10143, 0x5a1},
+	{ 0x11043, 0x5a1},
+	{ 0x11143, 0x5a1},
+	{ 0x1200b2, 0x10c},
+	{ 0x110043, 0x5a1},
+	{ 0x110143, 0x5a1},
+	{ 0x111043, 0x5a1},
+	{ 0x111143, 0x5a1},
+	{ 0x2200b2, 0x10c},
+	{ 0x210043, 0x5a1},
+	{ 0x210143, 0x5a1},
+	{ 0x211043, 0x5a1},
+	{ 0x211143, 0x5a1},
+	{ 0x200fa, 0x2},
+	{ 0x1200fa, 0x2},
+	{ 0x2200fa, 0x2},
+	{ 0x20019, 0x1},
+	{ 0x120019, 0x1},
+	{ 0x220019, 0x1},
+	{ 0x200f0, 0x600},
+	{ 0x200f1, 0x0},
+	{ 0x200f2, 0x4444},
+	{ 0x200f3, 0x8888},
+	{ 0x200f4, 0x5655},
+	{ 0x200f5, 0x0},
+	{ 0x200f6, 0x0},
+	{ 0x200f7, 0xf000},
+	{ 0x1004a, 0x500},
+	{ 0x1104a, 0x500},
+	{ 0x20025, 0x0},
+	{ 0x2002d, 0x0},
+	{ 0x12002d, 0x0},
+	{ 0x22002d, 0x0},
+	{ 0x2002c, 0x0},
+	/* workaround STAR_3141216 marker */
+	{ 0x20021, 0x0},
+	/* workaround STAR_3975199 marker */
+	{ 0x200c7, 0x21},
+	/* workaround STAR_3975199 marker */
+	{ 0x200ca, 0x24},
+	/* workaround STAR_3975199 marker */
+	{ 0x1200c7, 0x21},
+	/* workaround STAR_3975199 marker */
+	{ 0x1200ca, 0x24},
+};
+
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x1005f, 0x0},
+	{ 0x1015f, 0x0},
+	{ 0x1105f, 0x0},
+	{ 0x1115f, 0x0},
+	{ 0x11005f, 0x0},
+	{ 0x11015f, 0x0},
+	{ 0x11105f, 0x0},
+	{ 0x11115f, 0x0},
+	{ 0x21005f, 0x0},
+	{ 0x21015f, 0x0},
+	{ 0x21105f, 0x0},
+	{ 0x21115f, 0x0},
+	{ 0x55, 0x0},
+	{ 0x1055, 0x0},
+	{ 0x2055, 0x0},
+	{ 0x200c5, 0x0},
+	{ 0x1200c5, 0x0},
+	{ 0x2200c5, 0x0},
+	{ 0x2002e, 0x0},
+	{ 0x12002e, 0x0},
+	{ 0x22002e, 0x0},
+	{ 0x90204, 0x0},
+	{ 0x190204, 0x0},
+	{ 0x290204, 0x0},
+	{ 0x20024, 0x0},
+	{ 0x2003a, 0x0},
+	{ 0x2007d, 0x0},
+	{ 0x2007c, 0x0},
+	{ 0x120024, 0x0},
+	{ 0x12007d, 0x0},
+	{ 0x12007c, 0x0},
+	{ 0x220024, 0x0},
+	{ 0x22007d, 0x0},
+	{ 0x22007c, 0x0},
+	{ 0x20056, 0x0},
+	{ 0x120056, 0x0},
+	{ 0x220056, 0x0},
+	{ 0x1004d, 0x0},
+	{ 0x1014d, 0x0},
+	{ 0x1104d, 0x0},
+	{ 0x1114d, 0x0},
+	{ 0x11004d, 0x0},
+	{ 0x11014d, 0x0},
+	{ 0x11104d, 0x0},
+	{ 0x11114d, 0x0},
+	{ 0x21004d, 0x0},
+	{ 0x21014d, 0x0},
+	{ 0x21104d, 0x0},
+	{ 0x21114d, 0x0},
+	{ 0x10049, 0x0},
+	{ 0x10149, 0x0},
+	{ 0x11049, 0x0},
+	{ 0x11149, 0x0},
+	{ 0x110049, 0x0},
+	{ 0x110149, 0x0},
+	{ 0x111049, 0x0},
+	{ 0x111149, 0x0},
+	{ 0x210049, 0x0},
+	{ 0x210149, 0x0},
+	{ 0x211049, 0x0},
+	{ 0x211149, 0x0},
+	{ 0x43, 0x0},
+	{ 0x1043, 0x0},
+	{ 0x2043, 0x0},
+	{ 0x20018, 0x0},
+	{ 0x20075, 0x0},
+	{ 0x20050, 0x0},
+	{ 0x2009b, 0x0},
+	{ 0x20008, 0x0},
+	{ 0x120008, 0x0},
+	{ 0x220008, 0x0},
+	{ 0x20088, 0x0},
+	{ 0x200b2, 0x0},
+	{ 0x10043, 0x0},
+	{ 0x10143, 0x0},
+	{ 0x11043, 0x0},
+	{ 0x11143, 0x0},
+	{ 0x1200b2, 0x0},
+	{ 0x110043, 0x0},
+	{ 0x110143, 0x0},
+	{ 0x111043, 0x0},
+	{ 0x111143, 0x0},
+	{ 0x2200b2, 0x0},
+	{ 0x210043, 0x0},
+	{ 0x210143, 0x0},
+	{ 0x211043, 0x0},
+	{ 0x211143, 0x0},
+	{ 0x200fa, 0x0},
+	{ 0x1200fa, 0x0},
+	{ 0x2200fa, 0x0},
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+	{ 0x111b4, 0x0},
+	{ 0x112b4, 0x0},
+	{ 0x113b4, 0x0},
+	{ 0x114b4, 0x0},
+	{ 0x115b4, 0x0},
+	{ 0x116b4, 0x0},
+	{ 0x117b4, 0x0},
+	{ 0x118b4, 0x0},
+	{ 0x20089, 0x0},
+	{ 0xc0080, 0x0},
+	{ 0x200cb, 0x0},
+	{ 0x10068, 0x0},
+	{ 0x10069, 0x0},
+	{ 0x10168, 0x0},
+	{ 0x10169, 0x0},
+	{ 0x10268, 0x0},
+	{ 0x10269, 0x0},
+	{ 0x10368, 0x0},
+	{ 0x10369, 0x0},
+	{ 0x10468, 0x0},
+	{ 0x10469, 0x0},
+	{ 0x10568, 0x0},
+	{ 0x10569, 0x0},
+	{ 0x10668, 0x0},
+	{ 0x10669, 0x0},
+	{ 0x10768, 0x0},
+	{ 0x10769, 0x0},
+	{ 0x10868, 0x0},
+	{ 0x10869, 0x0},
+	{ 0x100aa, 0x0},
+	{ 0x10062, 0x0},
+	{ 0x10001, 0x0},
+	{ 0x100a0, 0x0},
+	{ 0x100a1, 0x0},
+	{ 0x100a2, 0x0},
+	{ 0x100a3, 0x0},
+	{ 0x100a4, 0x0},
+	{ 0x100a5, 0x0},
+	{ 0x100a6, 0x0},
+	{ 0x100a7, 0x0},
+	{ 0x11068, 0x0},
+	{ 0x11069, 0x0},
+	{ 0x11168, 0x0},
+	{ 0x11169, 0x0},
+	{ 0x11268, 0x0},
+	{ 0x11269, 0x0},
+	{ 0x11368, 0x0},
+	{ 0x11369, 0x0},
+	{ 0x11468, 0x0},
+	{ 0x11469, 0x0},
+	{ 0x11568, 0x0},
+	{ 0x11569, 0x0},
+	{ 0x11668, 0x0},
+	{ 0x11669, 0x0},
+	{ 0x11768, 0x0},
+	{ 0x11769, 0x0},
+	{ 0x11868, 0x0},
+	{ 0x11869, 0x0},
+	{ 0x110aa, 0x0},
+	{ 0x11062, 0x0},
+	{ 0x11001, 0x0},
+	{ 0x110a0, 0x0},
+	{ 0x110a1, 0x0},
+	{ 0x110a2, 0x0},
+	{ 0x110a3, 0x0},
+	{ 0x110a4, 0x0},
+	{ 0x110a5, 0x0},
+	{ 0x110a6, 0x0},
+	{ 0x110a7, 0x0},
+	{ 0x80, 0x0},
+	{ 0x1080, 0x0},
+	{ 0x2080, 0x0},
+	{ 0x10020, 0x0},
+	{ 0x10080, 0x0},
+	{ 0x10081, 0x0},
+	{ 0x100d0, 0x0},
+	{ 0x100d1, 0x0},
+	{ 0x1008c, 0x0},
+	{ 0x1008d, 0x0},
+	{ 0x10180, 0x0},
+	{ 0x10181, 0x0},
+	{ 0x101d0, 0x0},
+	{ 0x101d1, 0x0},
+	{ 0x1018c, 0x0},
+	{ 0x1018d, 0x0},
+	{ 0x100c0, 0x0},
+	{ 0x100c1, 0x0},
+	{ 0x101c0, 0x0},
+	{ 0x101c1, 0x0},
+	{ 0x102c0, 0x0},
+	{ 0x102c1, 0x0},
+	{ 0x103c0, 0x0},
+	{ 0x103c1, 0x0},
+	{ 0x104c0, 0x0},
+	{ 0x104c1, 0x0},
+	{ 0x105c0, 0x0},
+	{ 0x105c1, 0x0},
+	{ 0x106c0, 0x0},
+	{ 0x106c1, 0x0},
+	{ 0x107c0, 0x0},
+	{ 0x107c1, 0x0},
+	{ 0x108c0, 0x0},
+	{ 0x108c1, 0x0},
+	{ 0x100ae, 0x0},
+	{ 0x100af, 0x0},
+	{ 0x11020, 0x0},
+	{ 0x11080, 0x0},
+	{ 0x11081, 0x0},
+	{ 0x110d0, 0x0},
+	{ 0x110d1, 0x0},
+	{ 0x1108c, 0x0},
+	{ 0x1108d, 0x0},
+	{ 0x11180, 0x0},
+	{ 0x11181, 0x0},
+	{ 0x111d0, 0x0},
+	{ 0x111d1, 0x0},
+	{ 0x1118c, 0x0},
+	{ 0x1118d, 0x0},
+	{ 0x110c0, 0x0},
+	{ 0x110c1, 0x0},
+	{ 0x111c0, 0x0},
+	{ 0x111c1, 0x0},
+	{ 0x112c0, 0x0},
+	{ 0x112c1, 0x0},
+	{ 0x113c0, 0x0},
+	{ 0x113c1, 0x0},
+	{ 0x114c0, 0x0},
+	{ 0x114c1, 0x0},
+	{ 0x115c0, 0x0},
+	{ 0x115c1, 0x0},
+	{ 0x116c0, 0x0},
+	{ 0x116c1, 0x0},
+	{ 0x117c0, 0x0},
+	{ 0x117c1, 0x0},
+	{ 0x118c0, 0x0},
+	{ 0x118c1, 0x0},
+	{ 0x110ae, 0x0},
+	{ 0x110af, 0x0},
+	{ 0x90201, 0x0},
+	{ 0x90202, 0x0},
+	{ 0x90203, 0x0},
+	{ 0x90205, 0x0},
+	{ 0x90206, 0x0},
+	{ 0x90207, 0x0},
+	{ 0x90208, 0x0},
+	{ 0x20020, 0x0},
+	{ 0x100080, 0x0},
+	{ 0x101080, 0x0},
+	{ 0x102080, 0x0},
+	{ 0x110020, 0x0},
+	{ 0x110080, 0x0},
+	{ 0x110081, 0x0},
+	{ 0x1100d0, 0x0},
+	{ 0x1100d1, 0x0},
+	{ 0x11008c, 0x0},
+	{ 0x11008d, 0x0},
+	{ 0x110180, 0x0},
+	{ 0x110181, 0x0},
+	{ 0x1101d0, 0x0},
+	{ 0x1101d1, 0x0},
+	{ 0x11018c, 0x0},
+	{ 0x11018d, 0x0},
+	{ 0x1100c0, 0x0},
+	{ 0x1100c1, 0x0},
+	{ 0x1101c0, 0x0},
+	{ 0x1101c1, 0x0},
+	{ 0x1102c0, 0x0},
+	{ 0x1102c1, 0x0},
+	{ 0x1103c0, 0x0},
+	{ 0x1103c1, 0x0},
+	{ 0x1104c0, 0x0},
+	{ 0x1104c1, 0x0},
+	{ 0x1105c0, 0x0},
+	{ 0x1105c1, 0x0},
+	{ 0x1106c0, 0x0},
+	{ 0x1106c1, 0x0},
+	{ 0x1107c0, 0x0},
+	{ 0x1107c1, 0x0},
+	{ 0x1108c0, 0x0},
+	{ 0x1108c1, 0x0},
+	{ 0x1100ae, 0x0},
+	{ 0x1100af, 0x0},
+	{ 0x111020, 0x0},
+	{ 0x111080, 0x0},
+	{ 0x111081, 0x0},
+	{ 0x1110d0, 0x0},
+	{ 0x1110d1, 0x0},
+	{ 0x11108c, 0x0},
+	{ 0x11108d, 0x0},
+	{ 0x111180, 0x0},
+	{ 0x111181, 0x0},
+	{ 0x1111d0, 0x0},
+	{ 0x1111d1, 0x0},
+	{ 0x11118c, 0x0},
+	{ 0x11118d, 0x0},
+	{ 0x1110c0, 0x0},
+	{ 0x1110c1, 0x0},
+	{ 0x1111c0, 0x0},
+	{ 0x1111c1, 0x0},
+	{ 0x1112c0, 0x0},
+	{ 0x1112c1, 0x0},
+	{ 0x1113c0, 0x0},
+	{ 0x1113c1, 0x0},
+	{ 0x1114c0, 0x0},
+	{ 0x1114c1, 0x0},
+	{ 0x1115c0, 0x0},
+	{ 0x1115c1, 0x0},
+	{ 0x1116c0, 0x0},
+	{ 0x1116c1, 0x0},
+	{ 0x1117c0, 0x0},
+	{ 0x1117c1, 0x0},
+	{ 0x1118c0, 0x0},
+	{ 0x1118c1, 0x0},
+	{ 0x1110ae, 0x0},
+	{ 0x1110af, 0x0},
+	{ 0x190201, 0x0},
+	{ 0x190202, 0x0},
+	{ 0x190203, 0x0},
+	{ 0x190205, 0x0},
+	{ 0x190206, 0x0},
+	{ 0x190207, 0x0},
+	{ 0x190208, 0x0},
+	{ 0x120020, 0x0},
+	{ 0x200080, 0x0},
+	{ 0x201080, 0x0},
+	{ 0x202080, 0x0},
+	{ 0x210020, 0x0},
+	{ 0x210080, 0x0},
+	{ 0x210081, 0x0},
+	{ 0x2100d0, 0x0},
+	{ 0x2100d1, 0x0},
+	{ 0x21008c, 0x0},
+	{ 0x21008d, 0x0},
+	{ 0x210180, 0x0},
+	{ 0x210181, 0x0},
+	{ 0x2101d0, 0x0},
+	{ 0x2101d1, 0x0},
+	{ 0x21018c, 0x0},
+	{ 0x21018d, 0x0},
+	{ 0x2100c0, 0x0},
+	{ 0x2100c1, 0x0},
+	{ 0x2101c0, 0x0},
+	{ 0x2101c1, 0x0},
+	{ 0x2102c0, 0x0},
+	{ 0x2102c1, 0x0},
+	{ 0x2103c0, 0x0},
+	{ 0x2103c1, 0x0},
+	{ 0x2104c0, 0x0},
+	{ 0x2104c1, 0x0},
+	{ 0x2105c0, 0x0},
+	{ 0x2105c1, 0x0},
+	{ 0x2106c0, 0x0},
+	{ 0x2106c1, 0x0},
+	{ 0x2107c0, 0x0},
+	{ 0x2107c1, 0x0},
+	{ 0x2108c0, 0x0},
+	{ 0x2108c1, 0x0},
+	{ 0x2100ae, 0x0},
+	{ 0x2100af, 0x0},
+	{ 0x211020, 0x0},
+	{ 0x211080, 0x0},
+	{ 0x211081, 0x0},
+	{ 0x2110d0, 0x0},
+	{ 0x2110d1, 0x0},
+	{ 0x21108c, 0x0},
+	{ 0x21108d, 0x0},
+	{ 0x211180, 0x0},
+	{ 0x211181, 0x0},
+	{ 0x2111d0, 0x0},
+	{ 0x2111d1, 0x0},
+	{ 0x21118c, 0x0},
+	{ 0x21118d, 0x0},
+	{ 0x2110c0, 0x0},
+	{ 0x2110c1, 0x0},
+	{ 0x2111c0, 0x0},
+	{ 0x2111c1, 0x0},
+	{ 0x2112c0, 0x0},
+	{ 0x2112c1, 0x0},
+	{ 0x2113c0, 0x0},
+	{ 0x2113c1, 0x0},
+	{ 0x2114c0, 0x0},
+	{ 0x2114c1, 0x0},
+	{ 0x2115c0, 0x0},
+	{ 0x2115c1, 0x0},
+	{ 0x2116c0, 0x0},
+	{ 0x2116c1, 0x0},
+	{ 0x2117c0, 0x0},
+	{ 0x2117c1, 0x0},
+	{ 0x2118c0, 0x0},
+	{ 0x2118c1, 0x0},
+	{ 0x2110ae, 0x0},
+	{ 0x2110af, 0x0},
+	{ 0x290201, 0x0},
+	{ 0x290202, 0x0},
+	{ 0x290203, 0x0},
+	{ 0x290205, 0x0},
+	{ 0x290206, 0x0},
+	{ 0x290207, 0x0},
+	{ 0x290208, 0x0},
+	{ 0x220020, 0x0},
+	{ 0x20077, 0x0},
+	{ 0x20072, 0x0},
+	{ 0x20073, 0x0},
+	{ 0x400c0, 0x0},
+	{ 0x10040, 0x0},
+	{ 0x10140, 0x0},
+	{ 0x10240, 0x0},
+	{ 0x10340, 0x0},
+	{ 0x10440, 0x0},
+	{ 0x10540, 0x0},
+	{ 0x10640, 0x0},
+	{ 0x10740, 0x0},
+	{ 0x10840, 0x0},
+	{ 0x11040, 0x0},
+	{ 0x11140, 0x0},
+	{ 0x11240, 0x0},
+	{ 0x11340, 0x0},
+	{ 0x11440, 0x0},
+	{ 0x11540, 0x0},
+	{ 0x11640, 0x0},
+	{ 0x11740, 0x0},
+	{ 0x11840, 0x0},
+};
+
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0},
+	{ 0x54003, 0xe94},
+	{ 0x54004, 0x4},
+	{ 0x54006, 0x15},
+	{ 0x54008, 0x131f},
+	{ 0x54009, 0xc8},
+	{ 0x5400b, 0x4},
+	{ 0x5400d, 0x100},
+	{ 0x5400f, 0x100},
+	{ 0x54012, 0x310},
+	{ 0x54019, 0x36e4},
+	{ 0x5401a, 0x32},
+	{ 0x5401b, 0x1126},
+	{ 0x5401c, 0x1108},
+	{ 0x5401e, 0x4},
+	{ 0x5401f, 0x36e4},
+	{ 0x54020, 0x32},
+	{ 0x54021, 0x1126},
+	{ 0x54022, 0x1108},
+	{ 0x54024, 0x4},
+	{ 0x54032, 0xe400},
+	{ 0x54033, 0x3236},
+	{ 0x54034, 0x2600},
+	{ 0x54035, 0x811},
+	{ 0x54036, 0x11},
+	{ 0x54037, 0x400},
+	{ 0x54038, 0xe400},
+	{ 0x54039, 0x3236},
+	{ 0x5403a, 0x2600},
+	{ 0x5403b, 0x811},
+	{ 0x5403c, 0x11},
+	{ 0x5403d, 0x400},
+	{ 0xd0000, 0x1},
+};
+
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0},
+	{ 0x54002, 0x1},
+	{ 0x54003, 0x74a},
+	{ 0x54004, 0x4},
+	{ 0x54006, 0x15},
+	{ 0x54008, 0x121f},
+	{ 0x54009, 0xc8},
+	{ 0x5400b, 0x4},
+	{ 0x5400d, 0x100},
+	{ 0x5400f, 0x100},
+	{ 0x54012, 0x310},
+	{ 0x54019, 0x1bb4},
+	{ 0x5401a, 0x32},
+	{ 0x5401b, 0x1126},
+	{ 0x5401c, 0x1108},
+	{ 0x5401e, 0x4},
+	{ 0x5401f, 0x1bb4},
+	{ 0x54020, 0x32},
+	{ 0x54021, 0x1126},
+	{ 0x54022, 0x1108},
+	{ 0x54024, 0x4},
+	{ 0x54032, 0xb400},
+	{ 0x54033, 0x321b},
+	{ 0x54034, 0x2600},
+	{ 0x54035, 0x811},
+	{ 0x54036, 0x11},
+	{ 0x54037, 0x400},
+	{ 0x54038, 0xb400},
+	{ 0x54039, 0x321b},
+	{ 0x5403a, 0x2600},
+	{ 0x5403b, 0x811},
+	{ 0x5403c, 0x11},
+	{ 0x5403d, 0x400},
+	{ 0xd0000, 0x1},
+};
+
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0},
+	{ 0x54002, 0x102},
+	{ 0x54003, 0x270},
+	{ 0x54004, 0x4},
+	{ 0x54006, 0x15},
+	{ 0x54008, 0x121f},
+	{ 0x54009, 0xc8},
+	{ 0x5400b, 0x4},
+	{ 0x5400d, 0x100},
+	{ 0x5400f, 0x100},
+	{ 0x54012, 0x310},
+	{ 0x54019, 0x994},
+	{ 0x5401a, 0x32},
+	{ 0x5401b, 0x1126},
+	{ 0x5401c, 0x1100},
+	{ 0x5401e, 0x4},
+	{ 0x5401f, 0x994},
+	{ 0x54020, 0x32},
+	{ 0x54021, 0x1126},
+	{ 0x54022, 0x1100},
+	{ 0x54024, 0x4},
+	{ 0x54032, 0x9400},
+	{ 0x54033, 0x3209},
+	{ 0x54034, 0x2600},
+	{ 0x54035, 0x11},
+	{ 0x54036, 0x11},
+	{ 0x54037, 0x400},
+	{ 0x54038, 0x9400},
+	{ 0x54039, 0x3209},
+	{ 0x5403a, 0x2600},
+	{ 0x5403b, 0x11},
+	{ 0x5403c, 0x11},
+	{ 0x5403d, 0x400},
+	{ 0xd0000, 0x1},
+};
+
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0},
+	{ 0x54003, 0xe94},
+	{ 0x54004, 0x4},
+	{ 0x54006, 0x15},
+	{ 0x54008, 0x61},
+	{ 0x54009, 0xc8},
+	{ 0x5400b, 0x4},
+	{ 0x5400d, 0x100},
+	{ 0x5400f, 0x100},
+	{ 0x54010, 0x2080},
+	{ 0x54012, 0x310},
+	{ 0x54019, 0x36e4},
+	{ 0x5401a, 0x32},
+	{ 0x5401b, 0x1126},
+	{ 0x5401c, 0x1108},
+	{ 0x5401e, 0x4},
+	{ 0x5401f, 0x36e4},
+	{ 0x54020, 0x32},
+	{ 0x54021, 0x1126},
+	{ 0x54022, 0x1108},
+	{ 0x54024, 0x4},
+	{ 0x54032, 0xe400},
+	{ 0x54033, 0x3236},
+	{ 0x54034, 0x2600},
+	{ 0x54035, 0x811},
+	{ 0x54036, 0x11},
+	{ 0x54037, 0x400},
+	{ 0x54038, 0xe400},
+	{ 0x54039, 0x3236},
+	{ 0x5403a, 0x2600},
+	{ 0x5403b, 0x811},
+	{ 0x5403c, 0x11},
+	{ 0x5403d, 0x400},
+	{ 0xd0000, 0x1},
+};
+
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0},
+	{ 0x90000, 0x10},
+	{ 0x90001, 0x400},
+	{ 0x90002, 0x10e},
+	{ 0x90003, 0x0},
+	{ 0x90004, 0x0},
+	{ 0x90005, 0x8},
+	{ 0x90029, 0xb},
+	{ 0x9002a, 0x480},
+	{ 0x9002b, 0x109},
+	{ 0x9002c, 0x8},
+	{ 0x9002d, 0x448},
+	{ 0x9002e, 0x139},
+	{ 0x9002f, 0x8},
+	{ 0x90030, 0x478},
+	{ 0x90031, 0x109},
+	{ 0x90032, 0x0},
+	{ 0x90033, 0xe8},
+	{ 0x90034, 0x109},
+	{ 0x90035, 0x2},
+	{ 0x90036, 0x10},
+	{ 0x90037, 0x139},
+	{ 0x90038, 0xb},
+	{ 0x90039, 0x7c0},
+	{ 0x9003a, 0x139},
+	{ 0x9003b, 0x44},
+	{ 0x9003c, 0x633},
+	{ 0x9003d, 0x159},
+	{ 0x9003e, 0x14f},
+	{ 0x9003f, 0x630},
+	{ 0x90040, 0x159},
+	{ 0x90041, 0x47},
+	{ 0x90042, 0x633},
+	{ 0x90043, 0x149},
+	{ 0x90044, 0x4f},
+	{ 0x90045, 0x633},
+	{ 0x90046, 0x179},
+	{ 0x90047, 0x8},
+	{ 0x90048, 0xe0},
+	{ 0x90049, 0x109},
+	{ 0x9004a, 0x0},
+	{ 0x9004b, 0x7c8},
+	{ 0x9004c, 0x109},
+	{ 0x9004d, 0x0},
+	{ 0x9004e, 0x1},
+	{ 0x9004f, 0x8},
+	{ 0x90050, 0x30},
+	{ 0x90051, 0x65a},
+	{ 0x90052, 0x9},
+	{ 0x90053, 0x0},
+	{ 0x90054, 0x45a},
+	{ 0x90055, 0x9},
+	{ 0x90056, 0x0},
+	{ 0x90057, 0x448},
+	{ 0x90058, 0x109},
+	{ 0x90059, 0x40},
+	{ 0x9005a, 0x633},
+	{ 0x9005b, 0x179},
+	{ 0x9005c, 0x1},
+	{ 0x9005d, 0x618},
+	{ 0x9005e, 0x109},
+	{ 0x9005f, 0x40c0},
+	{ 0x90060, 0x633},
+	{ 0x90061, 0x149},
+	{ 0x90062, 0x8},
+	{ 0x90063, 0x4},
+	{ 0x90064, 0x48},
+	{ 0x90065, 0x4040},
+	{ 0x90066, 0x633},
+	{ 0x90067, 0x149},
+	{ 0x90068, 0x0},
+	{ 0x90069, 0x4},
+	{ 0x9006a, 0x48},
+	{ 0x9006b, 0x40},
+	{ 0x9006c, 0x633},
+	{ 0x9006d, 0x149},
+	{ 0x9006e, 0x0},
+	{ 0x9006f, 0x658},
+	{ 0x90070, 0x109},
+	{ 0x90071, 0x10},
+	{ 0x90072, 0x4},
+	{ 0x90073, 0x18},
+	{ 0x90074, 0x0},
+	{ 0x90075, 0x4},
+	{ 0x90076, 0x78},
+	{ 0x90077, 0x549},
+	{ 0x90078, 0x633},
+	{ 0x90079, 0x159},
+	{ 0x9007a, 0xd49},
+	{ 0x9007b, 0x633},
+	{ 0x9007c, 0x159},
+	{ 0x9007d, 0x94a},
+	{ 0x9007e, 0x633},
+	{ 0x9007f, 0x159},
+	{ 0x90080, 0x441},
+	{ 0x90081, 0x633},
+	{ 0x90082, 0x149},
+	{ 0x90083, 0x42},
+	{ 0x90084, 0x633},
+	{ 0x90085, 0x149},
+	{ 0x90086, 0x1},
+	{ 0x90087, 0x633},
+	{ 0x90088, 0x149},
+	{ 0x90089, 0x0},
+	{ 0x9008a, 0xe0},
+	{ 0x9008b, 0x109},
+	{ 0x9008c, 0xa},
+	{ 0x9008d, 0x10},
+	{ 0x9008e, 0x109},
+	{ 0x9008f, 0x9},
+	{ 0x90090, 0x3c0},
+	{ 0x90091, 0x149},
+	{ 0x90092, 0x9},
+	{ 0x90093, 0x3c0},
+	{ 0x90094, 0x159},
+	{ 0x90095, 0x18},
+	{ 0x90096, 0x10},
+	{ 0x90097, 0x109},
+	{ 0x90098, 0x0},
+	{ 0x90099, 0x3c0},
+	{ 0x9009a, 0x109},
+	{ 0x9009b, 0x18},
+	{ 0x9009c, 0x4},
+	{ 0x9009d, 0x48},
+	{ 0x9009e, 0x18},
+	{ 0x9009f, 0x4},
+	{ 0x900a0, 0x58},
+	{ 0x900a1, 0xb},
+	{ 0x900a2, 0x10},
+	{ 0x900a3, 0x109},
+	{ 0x900a4, 0x1},
+	{ 0x900a5, 0x10},
+	{ 0x900a6, 0x109},
+	{ 0x900a7, 0x5},
+	{ 0x900a8, 0x7c0},
+	{ 0x900a9, 0x109},
+	{ 0x40000, 0x811},
+	{ 0x40020, 0x880},
+	{ 0x40040, 0x0},
+	{ 0x40060, 0x0},
+	{ 0x40001, 0x4008},
+	{ 0x40021, 0x83},
+	{ 0x40041, 0x4f},
+	{ 0x40061, 0x0},
+	{ 0x40002, 0x4040},
+	{ 0x40022, 0x83},
+	{ 0x40042, 0x51},
+	{ 0x40062, 0x0},
+	{ 0x40003, 0x811},
+	{ 0x40023, 0x880},
+	{ 0x40043, 0x0},
+	{ 0x40063, 0x0},
+	{ 0x40004, 0x720},
+	{ 0x40024, 0xf},
+	{ 0x40044, 0x1740},
+	{ 0x40064, 0x0},
+	{ 0x40005, 0x16},
+	{ 0x40025, 0x83},
+	{ 0x40045, 0x4b},
+	{ 0x40065, 0x0},
+	{ 0x40006, 0x716},
+	{ 0x40026, 0xf},
+	{ 0x40046, 0x2001},
+	{ 0x40066, 0x0},
+	{ 0x40007, 0x716},
+	{ 0x40027, 0xf},
+	{ 0x40047, 0x2800},
+	{ 0x40067, 0x0},
+	{ 0x40008, 0x716},
+	{ 0x40028, 0xf},
+	{ 0x40048, 0xf00},
+	{ 0x40068, 0x0},
+	{ 0x40009, 0x720},
+	{ 0x40029, 0xf},
+	{ 0x40049, 0x1400},
+	{ 0x40069, 0x0},
+	{ 0x4000a, 0xe08},
+	{ 0x4002a, 0xc15},
+	{ 0x4004a, 0x0},
+	{ 0x4006a, 0x0},
+	{ 0x4000b, 0x625},
+	{ 0x4002b, 0x15},
+	{ 0x4004b, 0x0},
+	{ 0x4006b, 0x0},
+	{ 0x4000c, 0x4028},
+	{ 0x4002c, 0x80},
+	{ 0x4004c, 0x0},
+	{ 0x4006c, 0x0},
+	{ 0x4000d, 0xe08},
+	{ 0x4002d, 0xc1a},
+	{ 0x4004d, 0x0},
+	{ 0x4006d, 0x0},
+	{ 0x4000e, 0x625},
+	{ 0x4002e, 0x1a},
+	{ 0x4004e, 0x0},
+	{ 0x4006e, 0x0},
+	{ 0x4000f, 0x4040},
+	{ 0x4002f, 0x80},
+	{ 0x4004f, 0x0},
+	{ 0x4006f, 0x0},
+	{ 0x40010, 0x2604},
+	{ 0x40030, 0x15},
+	{ 0x40050, 0x0},
+	{ 0x40070, 0x0},
+	{ 0x40011, 0x708},
+	{ 0x40031, 0x5},
+	{ 0x40051, 0x0},
+	{ 0x40071, 0x2002},
+	{ 0x40012, 0x8},
+	{ 0x40032, 0x80},
+	{ 0x40052, 0x0},
+	{ 0x40072, 0x0},
+	{ 0x40013, 0x2604},
+	{ 0x40033, 0x1a},
+	{ 0x40053, 0x0},
+	{ 0x40073, 0x0},
+	{ 0x40014, 0x708},
+	{ 0x40034, 0xa},
+	{ 0x40054, 0x0},
+	{ 0x40074, 0x2002},
+	{ 0x40015, 0x4040},
+	{ 0x40035, 0x80},
+	{ 0x40055, 0x0},
+	{ 0x40075, 0x0},
+	{ 0x40016, 0x60a},
+	{ 0x40036, 0x15},
+	{ 0x40056, 0x1200},
+	{ 0x40076, 0x0},
+	{ 0x40017, 0x61a},
+	{ 0x40037, 0x15},
+	{ 0x40057, 0x1300},
+	{ 0x40077, 0x0},
+	{ 0x40018, 0x60a},
+	{ 0x40038, 0x1a},
+	{ 0x40058, 0x1200},
+	{ 0x40078, 0x0},
+	{ 0x40019, 0x642},
+	{ 0x40039, 0x1a},
+	{ 0x40059, 0x1300},
+	{ 0x40079, 0x0},
+	{ 0x4001a, 0x4808},
+	{ 0x4003a, 0x880},
+	{ 0x4005a, 0x0},
+	{ 0x4007a, 0x0},
+	{ 0x900aa, 0x0},
+	{ 0x900ab, 0x790},
+	{ 0x900ac, 0x11a},
+	{ 0x900ad, 0x8},
+	{ 0x900ae, 0x7aa},
+	{ 0x900af, 0x2a},
+	{ 0x900b0, 0x10},
+	{ 0x900b1, 0x7b2},
+	{ 0x900b2, 0x2a},
+	{ 0x900b3, 0x0},
+	{ 0x900b4, 0x7c8},
+	{ 0x900b5, 0x109},
+	{ 0x900b6, 0x10},
+	{ 0x900b7, 0x10},
+	{ 0x900b8, 0x109},
+	{ 0x900b9, 0x10},
+	{ 0x900ba, 0x2a8},
+	{ 0x900bb, 0x129},
+	{ 0x900bc, 0x8},
+	{ 0x900bd, 0x370},
+	{ 0x900be, 0x129},
+	{ 0x900bf, 0xa},
+	{ 0x900c0, 0x3c8},
+	{ 0x900c1, 0x1a9},
+	{ 0x900c2, 0xc},
+	{ 0x900c3, 0x408},
+	{ 0x900c4, 0x199},
+	{ 0x900c5, 0x14},
+	{ 0x900c6, 0x790},
+	{ 0x900c7, 0x11a},
+	{ 0x900c8, 0x8},
+	{ 0x900c9, 0x4},
+	{ 0x900ca, 0x18},
+	{ 0x900cb, 0xe},
+	{ 0x900cc, 0x408},
+	{ 0x900cd, 0x199},
+	{ 0x900ce, 0x8},
+	{ 0x900cf, 0x8568},
+	{ 0x900d0, 0x108},
+	{ 0x900d1, 0x18},
+	{ 0x900d2, 0x790},
+	{ 0x900d3, 0x16a},
+	{ 0x900d4, 0x8},
+	{ 0x900d5, 0x1d8},
+	{ 0x900d6, 0x169},
+	{ 0x900d7, 0x10},
+	{ 0x900d8, 0x8558},
+	{ 0x900d9, 0x168},
+	{ 0x900da, 0x1ff8},
+	{ 0x900db, 0x85a8},
+	{ 0x900dc, 0x1e8},
+	{ 0x900dd, 0x50},
+	{ 0x900de, 0x798},
+	{ 0x900df, 0x16a},
+	{ 0x900e0, 0x60},
+	{ 0x900e1, 0x7a0},
+	{ 0x900e2, 0x16a},
+	{ 0x900e3, 0x8},
+	{ 0x900e4, 0x8310},
+	{ 0x900e5, 0x168},
+	{ 0x900e6, 0x8},
+	{ 0x900e7, 0xa310},
+	{ 0x900e8, 0x168},
+	{ 0x900e9, 0xa},
+	{ 0x900ea, 0x408},
+	{ 0x900eb, 0x169},
+	{ 0x900ec, 0x6e},
+	{ 0x900ed, 0x0},
+	{ 0x900ee, 0x68},
+	{ 0x900ef, 0x0},
+	{ 0x900f0, 0x408},
+	{ 0x900f1, 0x169},
+	{ 0x900f2, 0x0},
+	{ 0x900f3, 0x8310},
+	{ 0x900f4, 0x168},
+	{ 0x900f5, 0x0},
+	{ 0x900f6, 0xa310},
+	{ 0x900f7, 0x168},
+	{ 0x900f8, 0x1ff8},
+	{ 0x900f9, 0x85a8},
+	{ 0x900fa, 0x1e8},
+	{ 0x900fb, 0x68},
+	{ 0x900fc, 0x798},
+	{ 0x900fd, 0x16a},
+	{ 0x900fe, 0x78},
+	{ 0x900ff, 0x7a0},
+	{ 0x90100, 0x16a},
+	{ 0x90101, 0x68},
+	{ 0x90102, 0x790},
+	{ 0x90103, 0x16a},
+	{ 0x90104, 0x8},
+	{ 0x90105, 0x8b10},
+	{ 0x90106, 0x168},
+	{ 0x90107, 0x8},
+	{ 0x90108, 0xab10},
+	{ 0x90109, 0x168},
+	{ 0x9010a, 0xa},
+	{ 0x9010b, 0x408},
+	{ 0x9010c, 0x169},
+	{ 0x9010d, 0x58},
+	{ 0x9010e, 0x0},
+	{ 0x9010f, 0x68},
+	{ 0x90110, 0x0},
+	{ 0x90111, 0x408},
+	{ 0x90112, 0x169},
+	{ 0x90113, 0x0},
+	{ 0x90114, 0x8b10},
+	{ 0x90115, 0x168},
+	{ 0x90116, 0x1},
+	{ 0x90117, 0xab10},
+	{ 0x90118, 0x168},
+	{ 0x90119, 0x0},
+	{ 0x9011a, 0x1d8},
+	{ 0x9011b, 0x169},
+	{ 0x9011c, 0x80},
+	{ 0x9011d, 0x790},
+	{ 0x9011e, 0x16a},
+	{ 0x9011f, 0x18},
+	{ 0x90120, 0x7aa},
+	{ 0x90121, 0x6a},
+	{ 0x90122, 0xa},
+	{ 0x90123, 0x0},
+	{ 0x90124, 0x1e9},
+	{ 0x90125, 0x8},
+	{ 0x90126, 0x8080},
+	{ 0x90127, 0x108},
+	{ 0x90128, 0xf},
+	{ 0x90129, 0x408},
+	{ 0x9012a, 0x169},
+	{ 0x9012b, 0xc},
+	{ 0x9012c, 0x0},
+	{ 0x9012d, 0x68},
+	{ 0x9012e, 0x9},
+	{ 0x9012f, 0x0},
+	{ 0x90130, 0x1a9},
+	{ 0x90131, 0x0},
+	{ 0x90132, 0x408},
+	{ 0x90133, 0x169},
+	{ 0x90134, 0x0},
+	{ 0x90135, 0x8080},
+	{ 0x90136, 0x108},
+	{ 0x90137, 0x8},
+	{ 0x90138, 0x7aa},
+	{ 0x90139, 0x6a},
+	{ 0x9013a, 0x0},
+	{ 0x9013b, 0x8568},
+	{ 0x9013c, 0x108},
+	{ 0x9013d, 0xb7},
+	{ 0x9013e, 0x790},
+	{ 0x9013f, 0x16a},
+	{ 0x90140, 0x1f},
+	{ 0x90141, 0x0},
+	{ 0x90142, 0x68},
+	{ 0x90143, 0x8},
+	{ 0x90144, 0x8558},
+	{ 0x90145, 0x168},
+	{ 0x90146, 0xf},
+	{ 0x90147, 0x408},
+	{ 0x90148, 0x169},
+	{ 0x90149, 0xd},
+	{ 0x9014a, 0x0},
+	{ 0x9014b, 0x68},
+	{ 0x9014c, 0x0},
+	{ 0x9014d, 0x408},
+	{ 0x9014e, 0x169},
+	{ 0x9014f, 0x0},
+	{ 0x90150, 0x8558},
+	{ 0x90151, 0x168},
+	{ 0x90152, 0x8},
+	{ 0x90153, 0x3c8},
+	{ 0x90154, 0x1a9},
+	{ 0x90155, 0x3},
+	{ 0x90156, 0x370},
+	{ 0x90157, 0x129},
+	{ 0x90158, 0x20},
+	{ 0x90159, 0x2aa},
+	{ 0x9015a, 0x9},
+	{ 0x9015b, 0x8},
+	{ 0x9015c, 0xe8},
+	{ 0x9015d, 0x109},
+	{ 0x9015e, 0x0},
+	{ 0x9015f, 0x8140},
+	{ 0x90160, 0x10c},
+	{ 0x90161, 0x10},
+	{ 0x90162, 0x8138},
+	{ 0x90163, 0x104},
+	{ 0x90164, 0x8},
+	{ 0x90165, 0x448},
+	{ 0x90166, 0x109},
+	{ 0x90167, 0xf},
+	{ 0x90168, 0x7c0},
+	{ 0x90169, 0x109},
+	{ 0x9016a, 0x0},
+	{ 0x9016b, 0xe8},
+	{ 0x9016c, 0x109},
+	{ 0x9016d, 0x47},
+	{ 0x9016e, 0x630},
+	{ 0x9016f, 0x109},
+	{ 0x90170, 0x8},
+	{ 0x90171, 0x618},
+	{ 0x90172, 0x109},
+	{ 0x90173, 0x8},
+	{ 0x90174, 0xe0},
+	{ 0x90175, 0x109},
+	{ 0x90176, 0x0},
+	{ 0x90177, 0x7c8},
+	{ 0x90178, 0x109},
+	{ 0x90179, 0x8},
+	{ 0x9017a, 0x8140},
+	{ 0x9017b, 0x10c},
+	{ 0x9017c, 0x0},
+	{ 0x9017d, 0x478},
+	{ 0x9017e, 0x109},
+	{ 0x9017f, 0x0},
+	{ 0x90180, 0x1},
+	{ 0x90181, 0x8},
+	{ 0x90182, 0x8},
+	{ 0x90183, 0x4},
+	{ 0x90184, 0x0},
+	{ 0x90006, 0x8},
+	{ 0x90007, 0x7c8},
+	{ 0x90008, 0x109},
+	{ 0x90009, 0x0},
+	{ 0x9000a, 0x400},
+	{ 0x9000b, 0x106},
+	{ 0xd00e7, 0x400},
+	{ 0x90017, 0x0},
+	{ 0x9001f, 0x2b},
+	{ 0x90026, 0x69},
+	{ 0x400d0, 0x0},
+	{ 0x400d1, 0x101},
+	{ 0x400d2, 0x105},
+	{ 0x400d3, 0x107},
+	{ 0x400d4, 0x10f},
+	{ 0x400d5, 0x202},
+	{ 0x400d6, 0x20a},
+	{ 0x400d7, 0x20b},
+	{ 0x2003a, 0x2},
+	{ 0x200be, 0x3},
+	{ 0x2000b, 0x75},
+	{ 0x2000c, 0xe9},
+	{ 0x2000d, 0x91c},
+	{ 0x2000e, 0x2c},
+	{ 0x12000b, 0x3b},
+	{ 0x12000c, 0x74},
+	{ 0x12000d, 0x48e},
+	{ 0x12000e, 0x2c},
+	{ 0x22000b, 0x14},
+	{ 0x22000c, 0x27},
+	{ 0x22000d, 0x186},
+	{ 0x22000e, 0x10},
+	{ 0x9000c, 0x0},
+	{ 0x9000d, 0x173},
+	{ 0x9000e, 0x60},
+	{ 0x9000f, 0x6110},
+	{ 0x90010, 0x2152},
+	{ 0x90011, 0xdfbd},
+	{ 0x90012, 0x2060},
+	{ 0x90013, 0x6152},
+	{ 0x20010, 0x5a},
+	{ 0x20011, 0x3},
+	{ 0x120010, 0x5a},
+	{ 0x120011, 0x3},
+	{ 0x40080, 0xe0},
+	{ 0x40081, 0x12},
+	{ 0x40082, 0xe0},
+	{ 0x40083, 0x12},
+	{ 0x40084, 0xe0},
+	{ 0x40085, 0x12},
+	{ 0x140080, 0xe0},
+	{ 0x140081, 0x12},
+	{ 0x140082, 0xe0},
+	{ 0x140083, 0x12},
+	{ 0x140084, 0xe0},
+	{ 0x140085, 0x12},
+	{ 0x240080, 0xe0},
+	{ 0x240081, 0x12},
+	{ 0x240082, 0xe0},
+	{ 0x240083, 0x12},
+	{ 0x240084, 0xe0},
+	{ 0x240085, 0x12},
+	{ 0x400fd, 0xf},
+	{ 0x400f1, 0xe},
+	{ 0x10011, 0x1},
+	{ 0x10012, 0x1},
+	{ 0x10013, 0x180},
+	{ 0x10018, 0x1},
+	{ 0x10002, 0x6209},
+	{ 0x100b2, 0x1},
+	{ 0x101b4, 0x1},
+	{ 0x102b4, 0x1},
+	{ 0x103b4, 0x1},
+	{ 0x104b4, 0x1},
+	{ 0x105b4, 0x1},
+	{ 0x106b4, 0x1},
+	{ 0x107b4, 0x1},
+	{ 0x108b4, 0x1},
+	{ 0x11011, 0x1},
+	{ 0x11012, 0x1},
+	{ 0x11013, 0x180},
+	{ 0x11018, 0x1},
+	{ 0x11002, 0x6209},
+	{ 0x110b2, 0x1},
+	{ 0x111b4, 0x1},
+	{ 0x112b4, 0x1},
+	{ 0x113b4, 0x1},
+	{ 0x114b4, 0x1},
+	{ 0x115b4, 0x1},
+	{ 0x116b4, 0x1},
+	{ 0x117b4, 0x1},
+	{ 0x118b4, 0x1},
+	{ 0x20089, 0x1},
+	{ 0x20088, 0x19},
+	{ 0xc0080, 0x0},
+	/* workaround STAR_3256585 marker */
+	{ 0x2000b, 0x41a},
+	/* workaround STAR_3256585 marker */
+	{ 0x12000b, 0x20d},
+	/* workaround STAR_3256585 marker */
+	{ 0x22000b, 0xb0},
+	{ 0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3733mts 1D */
+		.drate = 3733,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1866mts 1D */
+		.drate = 1866,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3733mts 2D */
+		.drate = 3733,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2CS_2GB = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3733, 1866, 625, },
+	.fsp_cfg = ddr_dram_fsp_cfg,
+	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c
index 068091ba0e9..40054ff72d0 100644
--- a/board/nxp/imx93_frdm/spl.c
+++ b/board/nxp/imx93_frdm/spl.c
@@ -33,9 +33,10 @@ static struct _drams {
 	u8 mr8;
 	struct dram_timing_info *pdram_timing;
 	char *name;
-} frdm_drams[2] = {
+} frdm_drams[3] = {
 	{0x10, &dram_timing_1GB, "1GB DRAM" },
-	{0x18, &dram_timing_2GB, "2GB DRAM" },
+	{0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" },
+	{0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" },
 };
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env
index d669c6e3133..d14a1b6c9bd 100644
--- a/board/nxp/imx93_qsb/imx93_qsb.env
+++ b/board/nxp/imx93_qsb/imx93_qsb.env
@@ -10,6 +10,10 @@ fdt_addr_r=0x83000000
 fdt_addr=0x83000000
 fdtfile=DEFAULT_FDT_FILE
 image=Image
+ip_dyn=yes
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
 mmcpart=1
 mmcroot=/dev/mmcblk1p2 rootwait rw
diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c
index 4731b79b55d..02149afae87 100644
--- a/board/nxp/imx94_evk/imx94_evk.c
+++ b/board/nxp/imx94_evk/imx94_evk.c
@@ -7,7 +7,7 @@
 #include <fdt_support.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
-#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/sys_proto.h>
 
 int board_init(void)
 {
@@ -26,3 +26,11 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif
diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env
index 894f5975812..c2006c95529 100644
--- a/board/nxp/imx94_evk/imx94_evk.env
+++ b/board/nxp/imx94_evk/imx94_evk.env
@@ -19,7 +19,10 @@ initrd_addr=0x93800000
 emmc_dev=0
 sd_dev=1
 scriptaddr=0x93500000
+ip_dyn=yes
 kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 image=Image
 splashimage=0xA0000000
 console=ttyLP0,115200 earlycon
diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c
index 6eb0fff99f4..739a5f1f559 100644
--- a/board/nxp/imx94_evk/spl.c
+++ b/board/nxp/imx94_evk/spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  */
 
 #include <hang.h>
@@ -14,6 +14,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/qb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,6 +45,9 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
+
+	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
+		spl_imx_qb_save();
 }
 
 static void xspi_nor_reset(void)
diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c
index 2a61817939e..b5c2da032a8 100644
--- a/board/nxp/imx952_evk/imx952_evk.c
+++ b/board/nxp/imx952_evk/imx952_evk.c
@@ -24,3 +24,11 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif
diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env
index 6ecaf9724c1..07faeb9fc9a 100644
--- a/board/nxp/imx952_evk/imx952_evk.env
+++ b/board/nxp/imx952_evk/imx952_evk.env
@@ -52,7 +52,10 @@ initrd_addr=0x93800000
 emmc_dev=0
 sd_dev=1
 scriptaddr=0x93500000
+ip_dyn=yes
 kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 image=Image
 splashimage=0xA0000000
 console=ttyLP0,115200 earlycon
diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c
index de9256dc267..615c3b67fb6 100644
--- a/board/nxp/imx952_evk/spl.c
+++ b/board/nxp/imx952_evk/spl.c
@@ -8,6 +8,7 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/qb.h>
 #include <asm/sections.h>
 #include <hang.h>
 #include <init.h>
@@ -44,6 +45,9 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
+
+	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
+		spl_imx_qb_save();
 }
 
 static void xspi_nor_reset(void)
diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c
index 99a37e0593f..394d6fd459c 100644
--- a/board/nxp/imx95_evk/imx95_evk.c
+++ b/board/nxp/imx95_evk/imx95_evk.c
@@ -5,7 +5,7 @@
 
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
-#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/sys_proto.h>
 
 int board_late_init(void)
 {
@@ -14,3 +14,11 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif
diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env
index 19f9bd5c16e..1d63a74aefa 100644
--- a/board/nxp/imx95_evk/imx95_evk.env
+++ b/board/nxp/imx95_evk/imx95_evk.env
@@ -3,8 +3,11 @@ initrd_addr=0x93800000
 emmc_dev=0
 sd_dev=1
 scriptaddr=0x93500000
-kernel_addr_r=CONFIG_SYS_LOAD_ADDR
 image=Image
+ip_dyn=yes
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
 splashimage=0xA0000000
 console=ttyLP0,115200 earlycon
 fdt_addr_r=0x93000000
diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c
index 761a1a4a0f6..2fd69447e1e 100644
--- a/board/nxp/imx95_evk/spl.c
+++ b/board/nxp/imx95_evk/spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  */
 
 #include <hang.h>
@@ -13,6 +13,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/qb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,6 +42,9 @@ void spl_board_init(void)
 	ret = ele_start_rng();
 	if (ret)
 		printf("Fail to start RNG: %d\n", ret);
+
+	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
+		spl_imx_qb_save();
 }
 
 void board_init_f(ulong dummy)
diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c
index 11dbef84688..6843b33679d 100644
--- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c
+++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c
@@ -73,7 +73,7 @@ u32 spl_boot_device(void)
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	return 0;
 }
diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c
index 056489932ac..19d068fc626 100644
--- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c
+++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c
@@ -78,7 +78,7 @@ u32 spl_boot_device(void)
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	return 0;
 }
diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c
index 047aea8181a..3afd5ae2136 100644
--- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c
+++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c
@@ -73,7 +73,7 @@ u32 spl_boot_device(void)
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+	gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
 
 	return 0;
 }
diff --git a/board/nxp/ls1012ardb/Kconfig b/board/nxp/ls1012ardb/Kconfig
index bbe5ce21109..ff5a57aaa41 100644
--- a/board/nxp/ls1012ardb/Kconfig
+++ b/board/nxp/ls1012ardb/Kconfig
@@ -63,7 +63,7 @@ config SYS_BOARD
         default "ls1012ardb"
 
 config SYS_VENDOR
-        default "nxp"
+	default "nxp"
 
 config SYS_SOC
         default "fsl-layerscape"
diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c
index fd897e832c8..8d07f6110ce 100644
--- a/board/nxp/ls1021aqds/ddr.c
+++ b/board/nxp/ls1021aqds/ddr.c
@@ -192,8 +192,8 @@ int fsl_initdram(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c
index 007125358bd..e1e83137f4d 100644
--- a/board/nxp/ls1028a/ls1028a.c
+++ b/board/nxp/ls1028a/ls1028a.c
@@ -26,7 +26,9 @@
 #include <fdtdec.h>
 #include <miiphy.h>
 #include "../common/qixis.h"
+#ifdef CONFIG_FSL_ENETC
 #include "../drivers/net/fsl_enetc.h"
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -147,7 +149,7 @@ int board_early_init_f(void)
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
-	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_size(gd->dram[0].size + gd->dram[1].size, "");
 	print_ddr_info(0);
 }
 
@@ -200,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	ft_cpu_setup(blob, bd);
 
 	/* fixup DT for the two GPP DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env
new file mode 100644
index 00000000000..dc1cb01e50a
--- /dev/null
+++ b/board/nxp/ls1028a/ls1028ardb.env
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+board=ls1028ardb
+hwconfig=fsl_ddr:bank_intlv=auto
+fdtfile=fsl-ls1028a-rdb.dtb
+image=Image
+extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0
+othbootargs=video=1920x1080-32@60 cma=640M
+ramdisk_addr=0x800000
+ramdisk_size=0x2000000
+bootm_size=0x10000000
+kernel_addr=0x01000000
+scriptaddr=0x80000000
+scripthdraddr=0x80080000
+fdtheader_addr_r=0x80100000
+kernelheader_addr_r=0x80200000
+load_addr=0xa0000000
+kernel_addr_r=0x81000000
+fdt_addr_r=0x90000000
+ramdisk_addr_r=0xa0000000
+kernel_start=0x1000000
+kernelheader_start=0x600000
+kernel_load=0xa0000000
+kernel_size=0x2800000
+kernelheader_size=0x40000
+kernel_addr_sd=0x8000
+kernel_size_sd=0x14000
+kernelhdr_addr_sd=0x3000
+kernelhdr_size_sd=0x20
+console=ttyS0,115200
+console_dbg=earlycon=uart8250,mmio,0x21c0500
+boot_script_hdr=hdr_ls1028ardb_bs.out
+xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr
+	$kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r
+	$kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm
+	$load_addr#$board
+xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read
+	$load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000
+sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd
+	$kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd
+	$kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board
+sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr
+	0x4a00 0x200 && hdp load $load_addr 0x2000
+emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr
+	$kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r
+	$kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm
+	$load_addr#$board
+emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr
+	0x4a00 0x200 && hdp load $load_addr 0x2000
diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c
index 0f115c16232..dba93add698 100644
--- a/board/nxp/ls1043aqds/ls1043aqds.c
+++ b/board/nxp/ls1043aqds/ls1043aqds.c
@@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u8 reg;
 
 	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c
index bba041065b5..678c529cf55 100644
--- a/board/nxp/ls1043ardb/ls1043ardb.c
+++ b/board/nxp/ls1043ardb/ls1043ardb.c
@@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c
index 8889c24f1f0..6c35c0a4347 100644
--- a/board/nxp/ls1046afrwy/ls1046afrwy.c
+++ b/board/nxp/ls1046afrwy/ls1046afrwy.c
@@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c
index 679b0b2235f..ddd9993986f 100644
--- a/board/nxp/ls1046aqds/ls1046aqds.c
+++ b/board/nxp/ls1046aqds/ls1046aqds.c
@@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u8 reg;
 
 	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c
index 83b280f7646..6677e271029 100644
--- a/board/nxp/ls1046ardb/ls1046ardb.c
+++ b/board/nxp/ls1046ardb/ls1046ardb.c
@@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 	ft_cpu_setup(blob, bd);
diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c
index 5783dd8a403..1b477e83676 100644
--- a/board/nxp/ls1088a/ls1088a.c
+++ b/board/nxp/ls1088a/ls1088a.c
@@ -830,7 +830,7 @@ int board_init(void)
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
-	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_size(gd->dram[0].size + gd->dram[1].size, "");
 	print_ddr_info(0);
 }
 
@@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	/* fixup DT for the two GPP DDR banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		base[i] = gd->bd->bi_dram[i].start;
-		size[i] = gd->bd->bi_dram[i].size;
+		base[i] = gd->dram[i].start;
+		size[i] = gd->dram[i].size;
 	}
 
 #ifdef CONFIG_RESV_RAM
diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c
index aba0560181a..325dc817aaf 100644
--- a/board/nxp/ls2080aqds/ls2080aqds.c
+++ b/board/nxp/ls2080aqds/ls2080aqds.c
@@ -253,12 +253,12 @@ int misc_init_r(void)
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
-	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_size(gd->dram[0].size + gd->dram[1].size, "");
 	print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+	if (soc_has_dp_ddr() && gd->dram[2].size) {
 		puts("\nDP-DDR ");
-		print_size(gd->bd->bi_dram[2].size, "");
+		print_size(gd->dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
 #endif
@@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	ft_cpu_setup(blob, bd);
 
 	/* fixup DT for the two GPP DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c
index d08598d1c62..9dec818280b 100644
--- a/board/nxp/ls2080ardb/ls2080ardb.c
+++ b/board/nxp/ls2080ardb/ls2080ardb.c
@@ -359,12 +359,12 @@ int misc_init_r(void)
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
-	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_size(gd->dram[0].size + gd->dram[1].size, "");
 	print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+	if (soc_has_dp_ddr() && gd->dram[2].size) {
 		puts("\nDP-DDR ");
-		print_size(gd->bd->bi_dram[2].size, "");
+		print_size(gd->dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
 #endif
@@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	size = calloc(total_memory_banks, sizeof(u64));
 
 	/* fixup DT for the two GPP DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
+	base[0] = gd->dram[0].start;
+	size[0] = gd->dram[0].size;
+	base[1] = gd->dram[1].start;
+	size[1] = gd->dram[1].size;
 
 #ifdef CONFIG_RESV_RAM
 	/* reduce size if reserved memory is within this bank */
diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c
index b7a6ccf46aa..10729dfaf24 100644
--- a/board/nxp/lx2160a/lx2160a.c
+++ b/board/nxp/lx2160a/lx2160a.c
@@ -573,7 +573,7 @@ void detail_board_ddr_info(void)
 
 	puts("\nDDR    ");
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		ddr_size += gd->bd->bi_dram[i].size;
+		ddr_size += gd->dram[i].size;
 	print_size(ddr_size, "");
 	print_ddr_info(0);
 }
@@ -808,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	/* fixup DT for the three GPP DDR banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		base[i] = gd->bd->bi_dram[i].start;
-		size[i] = gd->bd->bi_dram[i].size;
+		base[i] = gd->dram[i].start;
+		size[i] = gd->dram[i].size;
 	}
 
 #ifdef CONFIG_RESV_RAM
diff --git a/board/nxp/mx6memcal/Kconfig b/board/nxp/mx6memcal/Kconfig
index a6c39d5e4d1..03d8422242f 100644
--- a/board/nxp/mx6memcal/Kconfig
+++ b/board/nxp/mx6memcal/Kconfig
@@ -35,30 +35,30 @@ choice
 	  The choices below reflect the most commonly used options
 	  for your UART.
 
-	config UART2_EIM_D26_27
-		bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
-		depends on SERIAL_CONSOLE_UART2
-		help
-		  Choose this configuration if you're using pads
-		  EIM_D26 and D27 for a console on UART2.
-		  This is typical for designs that are based on the
-		  NXP SABRELite.
-
-	config UART1_CSI0_DAT10_11
-		bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
-		depends on SERIAL_CONSOLE_UART1
-		help
-		  Choose this configuration if you're using pads
-		  CSI0_DAT10 and DAT11 for a console on UART1 as
-		  is done on the i.MX6 Wand board and i.MX6 SabreSD.
-
-	config UART1_UART1
-		bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
-		depends on SERIAL_CONSOLE_UART1
-		help
-		  Choose this configuration if you're using pads
-		  UART1_TXD/RXD for a console on UART1 as is done
-		  on most i.MX6SL designs.
+config UART2_EIM_D26_27
+	bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
+	depends on SERIAL_CONSOLE_UART2
+	help
+	  Choose this configuration if you're using pads
+	  EIM_D26 and D27 for a console on UART2.
+	  This is typical for designs that are based on the
+	  NXP SABRELite.
+
+config UART1_CSI0_DAT10_11
+	bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
+	depends on SERIAL_CONSOLE_UART1
+	help
+	  Choose this configuration if you're using pads
+	  CSI0_DAT10 and DAT11 for a console on UART1 as
+	  is done on the i.MX6 Wand board and i.MX6 SabreSD.
+
+config UART1_UART1
+	bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
+	depends on SERIAL_CONSOLE_UART1
+	help
+	  Choose this configuration if you're using pads
+	  UART1_TXD/RXD for a console on UART1 as is done
+	  on most i.MX6SL designs.
 
 endchoice
 
@@ -215,12 +215,12 @@ config REFR
 	range 0 7
 	default 7
 	help
-	   This selects the number of refreshes (-1) during each period.
-	   i.e.:
-	   0 == 1 refresh (tRFC)
-	   7 == 8 refreshes (tRFC*8)
-	   See the description of MDREF[REFR] in the reference manual for
-	   details.
+	  This selects the number of refreshes (-1) during each period.
+	  i.e.:
+	  0 == 1 refresh (tRFC)
+	  7 == 8 refreshes (tRFC*8)
+	  See the description of MDREF[REFR] in the reference manual for
+	  details.
 
 endmenu
 
diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env
new file mode 100644
index 00000000000..31a16905ef5
--- /dev/null
+++ b/board/nxp/mx6sabreauto/mx6sabreauto.env
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+console=ttymxc3
+
+#include <env/nxp/mx6sabre_common.env>
diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env
new file mode 100644
index 00000000000..3608e931665
--- /dev/null
+++ b/board/nxp/mx6sabresd/mx6sabresd.env
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+console=ttymxc0
+
+#include <env/nxp/mx6sabre_common.env>
diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env
new file mode 100644
index 00000000000..0fce3aaaa4e
--- /dev/null
+++ b/board/nxp/mx6ullevk/mx6ullevk.env
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+script=boot.scr
+image=zImage
+console=ttymxc0
+initrd_high=0xffffffff
+fdt_file=undefined
+fdt_addr=0x83000000
+boot_fdt=try
+ip_dyn=yes
+videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+mmcboot=echo Booting from mmc ...;
+	run mmcargs;
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if run loadfdt; then
+			bootz ${loadaddr} - ${fdt_addr};
+		else
+			if test ${boot_fdt} = try; then
+				bootz;
+			else
+				echo WARN: Cannot load the DT;
+			fi;
+		fi;
+	else
+		bootz;
+	fi;
+findfdt=if test $fdt_file = undefined; then
+		if test $board_name = ULZ-EVK && test $board_rev = 14X14; then
+			setenv fdt_file imx6ulz-14x14-evk.dtb;
+		fi;
+		if test $board_name = EVK && test $board_rev = 14X14; then
+			setenv fdt_file imx6ull-14x14-evk.dtb;
+		fi;
+		if test $fdt_file = undefined; then
+			echo WARNING: Could not determine dtb to use;
+		fi;
+	fi;
+netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs
+	ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	${get_cmd} ${image};
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+			bootz ${loadaddr} - ${fdt_addr};
+		else
+			if test ${boot_fdt} = try; then
+				bootz;
+			else
+				echo WARN: Cannot load the DT;
+			fi;
+		fi;
+	else
+		bootz;
+	fi;
diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env
new file mode 100644
index 00000000000..f5a384a61de
--- /dev/null
+++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+script=boot.scr
+image=zImage
+console=ttyLP0
+initrd_high=0xffffffff
+fdt_file=imx7ulp-evk.dtb
+fdt_addr=0x63000000
+boot_fdt=try
+earlycon=lpuart32,0x402D0010
+ip_dyn=yes
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+mmcpart=1
+mmcroot=/dev/mmcblk0p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+mmcboot=echo Booting from mmc ...;
+	run mmcargs;
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if run loadfdt; then
+			bootz ${loadaddr} - ${fdt_addr};
+		else
+			if test ${boot_fdt} = try; then
+				bootz;
+			else
+				echo WARN: Cannot load the DT;
+			fi;
+		fi;
+	else
+		bootz;
+	fi;
+netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs
+	ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	usb start;
+	${get_cmd} ${image};
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+			bootz ${loadaddr} - ${fdt_addr};
+		else
+			if test ${boot_fdt} = try; then
+				bootz;
+			else
+				echo WARN: Cannot load the DT;
+			fi;
+		fi;
+	else
+		bootz;
+	fi;
diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig
index e2ab80b6d4d..1b948fdc9ff 100644
--- a/board/out4/o4-imx6ull-nano/Kconfig
+++ b/board/out4/o4-imx6ull-nano/Kconfig
@@ -13,21 +13,21 @@ choice
 	prompt "Memory model"
 	default K4B4G1646D_BCMA
 	help
-	    Memory type setup.
+	  Memory type setup.
 
 	    Please choose correct memory model here.
 
 config K4B4G1646D_BCMA
 	bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)"
 	help
-	    Samsung DDR3 SDRAM
-	    K4B4G1646D-BCMA
+	  Samsung DDR3 SDRAM
+	  K4B4G1646D-BCMA
 
 config MT41K256M16HA_125E
 	bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)"
 	help
-	    Micron DDR3L SDRAM
-	    MT41K256M16HA-125:E
+	  Micron DDR3L SDRAM
+	  MT41K256M16HA-125:E
 
 endchoice
 
@@ -35,21 +35,21 @@ choice
 	prompt "Mainboard model"
 	default O4_IMX_NANO
 	help
-	    Mainboard setup.
+	  Mainboard setup.
 
 	    Please choose correct main board model here.
 
 config O4_IMX_NANO
 	bool "O4-iMX-NANO"
 	help
-	    A baseboard for EV-iMX280-NANO module:
-	    https://out4.ru/products/board/18-o4-imx-nano.html
+	  A baseboard for EV-iMX280-NANO module:
+	  https://out4.ru/products/board/18-o4-imx-nano.html
 
 config EV_IMX280_NANO_X_MB
 	bool "EV-IMX280-NANO-X-MB"
 	help
-	    A simple baseboard for EV-iMX280-NANO module:
-	    http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html
+	  A simple baseboard for EV-iMX280-NANO module:
+	  http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html
 
 endchoice
 
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index 6afd03086f7..87fa70632e5 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -2,14 +2,14 @@ config PHYTEC_SOM_DETECTION
 	bool "Support SoM detection for PHYTEC platforms"
 	select SPL_CRC8 if SPL
 	help
-	   Support of I2C EEPROM based SoM detection.
+	  Support of I2C EEPROM based SoM detection.
 
 config PHYTEC_SOM_DETECTION_BLOCKS
 	bool "Extend SoM detection with block support"
 	depends on PHYTEC_SOM_DETECTION
 	help
-	   Extend the I2C EEPROM based SoM detection with API v3. This API
-	   introduces blocks with different payloads.
+	  Extend the I2C EEPROM based SoM detection with API v3. This API
+	  introduces blocks with different payloads.
 
 config PHYTEC_IMX8M_SOM_DETECTION
 	bool "Support SoM detection for i.MX8M PHYTEC platforms"
@@ -35,8 +35,8 @@ config PHYTEC_AM62_SOM_DETECTION
 	depends on SPL_I2C && DM_I2C
 	default y
 	help
-	   Support of I2C EEPROM based SoM detection. Supported
-	   for PHYTEC AM62x boards.
+	  Support of I2C EEPROM based SoM detection. Supported
+	  for PHYTEC AM62x boards.
 
 config PHYTEC_AM62A_SOM_DETECTION
 	bool "Support SoM detection for AM62Ax PHYTEC platforms"
@@ -46,8 +46,8 @@ config PHYTEC_AM62A_SOM_DETECTION
 	depends on SPL_I2C && DM_I2C
 	default y
 	help
-	   Support of I2C EEPROM based SoM detection. Supported
-	   for PHYTEC AM62Ax boards.
+	  Support of I2C EEPROM based SoM detection. Supported
+	  for PHYTEC AM62Ax boards.
 
 config PHYTEC_AM64_SOM_DETECTION
 	bool "Support SoM detection for AM64x PHYTEC platforms"
@@ -57,8 +57,8 @@ config PHYTEC_AM64_SOM_DETECTION
 	depends on SPL_I2C && DM_I2C
 	default y
 	help
-	   Support of I2C EEPROM based SoM detection. Supported
-	   for PHYTEC AM64x boards.
+	  Support of I2C EEPROM based SoM detection. Supported
+	  for PHYTEC AM64x boards.
 
 config PHYTEC_EEPROM_BUS
 	int "Board EEPROM's I2C bus number"
diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig
index 282f4b79742..4bbe1a5ec3c 100644
--- a/board/phytec/common/k3/Kconfig
+++ b/board/phytec/common/k3/Kconfig
@@ -1,5 +1,5 @@
 config PHYTEC_K3_DDR_PATCH
 	bool "Patch DDR timings on PHYTEC K3 SoMs"
 	help
-	   Allow to override default DDR timings prior to
-	   DDRSS driver probing.
+	  Allow to override default DDR timings prior to
+	  DDRSS driver probing.
diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig
index 516dc8e2020..e7943c51dbc 100644
--- a/board/phytec/phycore_am62ax/Kconfig
+++ b/board/phytec/phycore_am62ax/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "phycore_am62ax"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am62ax"
@@ -24,7 +24,7 @@ config SYS_BOARD
        default "phycore_am62ax"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am62ax"
diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig
index ecee5873c0c..feacc3d6d40 100644
--- a/board/phytec/phycore_am62x/Kconfig
+++ b/board/phytec/phycore_am62x/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "phycore_am62x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am62x"
@@ -24,7 +24,7 @@ config SYS_BOARD
        default "phycore_am62x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am62x"
@@ -38,31 +38,31 @@ source "board/phytec/common/k3/Kconfig"
 endif
 
 config PHYCORE_AM62X_RAM_SIZE_FIX
-        bool "Set phyCORE-AM62x RAM size fix instead of detecting"
-        default false
-        help
-          RAM size is automatic being detected with the help of
-          the EEPROM introspection data. Set RAM size to a fix value
-          instead.
+	bool "Set phyCORE-AM62x RAM size fix instead of detecting"
+	default false
+	help
+	  RAM size is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM size to a fix value
+	  instead.
 
 choice
-        prompt "phyCORE-AM62x RAM size"
-        depends on PHYCORE_AM62X_RAM_SIZE_FIX
-        default PHYCORE_AM62X_RAM_SIZE_2GB
+	prompt "phyCORE-AM62x RAM size"
+	depends on PHYCORE_AM62X_RAM_SIZE_FIX
+	default PHYCORE_AM62X_RAM_SIZE_2GB
 
 config PHYCORE_AM62X_RAM_SIZE_1GB
-        bool "1GB RAM"
-        help
-          Set RAM size fix to 1GB for phyCORE-AM62x.
+	bool "1GB RAM"
+	help
+	  Set RAM size fix to 1GB for phyCORE-AM62x.
 
 config PHYCORE_AM62X_RAM_SIZE_2GB
-        bool "2GB RAM"
-        help
-          Set RAM size fix to 2GB for phyCORE-AM62x.
+	bool "2GB RAM"
+	help
+	  Set RAM size fix to 2GB for phyCORE-AM62x.
 
 config PHYCORE_AM62X_RAM_SIZE_4GB
-        bool "4GB RAM"
-        help
-          Set RAM size fix to 4GB for phyCORE-AM62x.
+	bool "4GB RAM"
+	help
+	  Set RAM size fix to 4GB for phyCORE-AM62x.
 
 endchoice
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c
index 3cdcbf2ecc9..6df521d789f 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -93,7 +93,7 @@ int dram_init_banksize(void)
 {
 	u8 ram_size;
 
-	memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);
+	memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);
 
 	if (!IS_ENABLED(CONFIG_CPU_V7R))
 		return fdtdec_setup_memory_banksize();
@@ -101,34 +101,34 @@ int dram_init_banksize(void)
 	ram_size = phytec_get_am62_ddr_size_default();
 	switch (ram_size) {
 	case EEPROM_RAM_SIZE_1GB:
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x40000000;
 		gd->ram_size = 0x40000000;
 		break;
 
 	case EEPROM_RAM_SIZE_2GB:
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x80000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x80000000;
 		gd->ram_size = 0x80000000;
 		break;
 
 	case EEPROM_RAM_SIZE_4GB:
 		/* Bank 0 declares the memory available in the DDR low region */
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x80000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x80000000;
 		gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
 		/* Bank 1 declares the memory available in the DDR upper region */
-		gd->bd->bi_dram[1].start = 0x880000000;
-		gd->bd->bi_dram[1].size = 0x80000000;
+		gd->dram[1].start = 0x880000000;
+		gd->dram[1].size = 0x80000000;
 		gd->ram_size = 0x100000000;
 #endif
 		break;
 	default:
 		/* Continue with default 2GB setup */
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x80000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x80000000;
 		gd->ram_size = 0x80000000;
 		printf("DDR size %d is not supported\n", ram_size);
 	}
@@ -186,8 +186,8 @@ int do_board_detect(void)
 	dram_init_banksize();
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = gd->bd->bi_dram[bank].start;
-		size[bank] = gd->bd->bi_dram[bank].size;
+		start[bank] = gd->dram[bank].start;
+		size[bank] = gd->dram[bank].size;
 	}
 
 	ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);
diff --git a/board/phytec/phycore_am62x/tifs-rm-cfg.yaml b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml
new file mode 100644
index 00000000000..8510fe9526e
--- /dev/null
+++ b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml
@@ -0,0 +1,867 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62X
+#
+
+---
+
+tifs-rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                -  # 1
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 2
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 3
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 4
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 5
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 6
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 7
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 8
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 9
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 10
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 11
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 12
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 13
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 14
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 15
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 16
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 17
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 18
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 19
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 20
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 21
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 22
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 23
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 24
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 25
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 26
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 27
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 28
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 29
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 30
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 31
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 32
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 824
+            reserved: 0
+    resasg_entries:
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1677
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1677
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 6
+            type: 1677
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 54
+            num_resource: 18
+            type: 1678
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 72
+            num_resource: 6
+            type: 1678
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 72
+            num_resource: 6
+            type: 1678
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 78
+            num_resource: 2
+            type: 1678
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 80
+            num_resource: 2
+            type: 1678
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 32
+            num_resource: 12
+            type: 1679
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 6
+            type: 1679
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 6
+            type: 1679
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 50
+            num_resource: 2
+            type: 1679
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 52
+            num_resource: 2
+            type: 1679
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1696
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1696
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 6
+            type: 1696
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1697
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1697
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 2
+            type: 1697
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 12
+            type: 1698
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 2
+            type: 1698
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 2
+            type: 1698
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5
+            num_resource: 35
+            type: 1802
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 168
+            num_resource: 7
+            type: 1802
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1024
+            type: 1807
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 29
+            type: 1808
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4608
+            num_resource: 99
+            type: 1809
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5120
+            num_resource: 24
+            type: 1810
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5632
+            num_resource: 51
+            type: 1811
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6144
+            num_resource: 51
+            type: 1812
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6656
+            num_resource: 51
+            type: 1813
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8192
+            num_resource: 32
+            type: 1814
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8704
+            num_resource: 32
+            type: 1815
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9216
+            num_resource: 32
+            type: 1816
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9728
+            num_resource: 22
+            type: 1817
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10240
+            num_resource: 22
+            type: 1818
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10752
+            num_resource: 22
+            type: 1819
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11264
+            num_resource: 28
+            type: 1820
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11776
+            num_resource: 28
+            type: 1821
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 12288
+            num_resource: 28
+            type: 1822
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1936
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1936
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1936
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 83
+            num_resource: 8
+            type: 1938
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 91
+            num_resource: 8
+            type: 1939
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 99
+            num_resource: 10
+            type: 1942
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 112
+            num_resource: 3
+            type: 1942
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 115
+            num_resource: 3
+            type: 1942
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1944
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1945
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1946
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1947
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1955
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1955
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1955
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 27
+            num_resource: 1
+            type: 1957
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 1
+            type: 1958
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1961
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1961
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1961
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1962
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1962
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1962
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 1
+            type: 1965
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1966
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 21
+            num_resource: 1
+            type: 1967
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1968
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 1
+            type: 1969
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1970
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 1
+            type: 1971
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1972
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 2112
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 2
+            type: 2122
+            host_id: 12
+            reserved: 0
diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig
index a709b71ba4d..a4d25b84b96 100644
--- a/board/phytec/phycore_am64x/Kconfig
+++ b/board/phytec/phycore_am64x/Kconfig
@@ -12,7 +12,7 @@ config SYS_BOARD
        default "phycore_am64x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am64x"
@@ -27,7 +27,7 @@ config SYS_BOARD
        default "phycore_am64x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am64x"
@@ -37,26 +37,26 @@ source "board/phytec/common/Kconfig"
 endif
 
 config PHYCORE_AM64X_RAM_SIZE_FIX
-        bool "Set phyCORE-AM64x RAM size fix instead of detecting"
-        default false
-        help
-          RAM size is automatic being detected with the help of
-          the EEPROM introspection data. Set RAM size to a fix value
-          instead.
+	bool "Set phyCORE-AM64x RAM size fix instead of detecting"
+	default false
+	help
+	  RAM size is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM size to a fix value
+	  instead.
 
 choice
-        prompt "phyCORE-AM64x RAM size"
-        depends on PHYCORE_AM64X_RAM_SIZE_FIX
-        default PHYCORE_AM64X_RAM_SIZE_2GB
+	prompt "phyCORE-AM64x RAM size"
+	depends on PHYCORE_AM64X_RAM_SIZE_FIX
+	default PHYCORE_AM64X_RAM_SIZE_2GB
 
 config PHYCORE_AM64X_RAM_SIZE_1GB
-        bool "1GB RAM"
-        help
-          Set RAM size fix to 1GB for phyCORE-AM64x.
+	bool "1GB RAM"
+	help
+	  Set RAM size fix to 1GB for phyCORE-AM64x.
 
 config PHYCORE_AM64X_RAM_SIZE_2GB
-        bool "2GB RAM"
-        help
-          Set RAM size fix to 2GB for phyCORE-AM64x.
+	bool "2GB RAM"
+	help
+	  Set RAM size fix to 2GB for phyCORE-AM64x.
 
 endchoice
diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c
index 114aa217023..5e077872152 100644
--- a/board/phytec/phycore_am64x/phycore-am64x.c
+++ b/board/phytec/phycore_am64x/phycore-am64x.c
@@ -66,7 +66,7 @@ int dram_init_banksize(void)
 {
 	u8 ram_size;
 
-	memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);
+	memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);
 
 	if (!IS_ENABLED(CONFIG_CPU_V7R))
 		return fdtdec_setup_memory_banksize();
@@ -74,21 +74,21 @@ int dram_init_banksize(void)
 	ram_size = phytec_get_am64_ddr_size_default();
 	switch (ram_size) {
 	case EEPROM_RAM_SIZE_1GB:
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x40000000;
 		gd->ram_size = 0x40000000;
 		break;
 
 	case EEPROM_RAM_SIZE_2GB:
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x80000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x80000000;
 		gd->ram_size = 0x80000000;
 		break;
 
 	default:
 		/* Continue with default 2GB setup */
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x80000000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x80000000;
 		gd->ram_size = 0x80000000;
 		printf("DDR size %d is not supported\n", ram_size);
 	}
@@ -109,8 +109,8 @@ int do_board_detect(void)
 	dram_init_banksize();
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = gd->bd->bi_dram[bank].start;
-		size[bank] = gd->bd->bi_dram[bank].size;
+		start[bank] = gd->dram[bank].start;
+		size[bank] = gd->dram[bank].size;
 	}
 
 	return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);
diff --git a/board/phytec/phycore_am68x/Kconfig b/board/phytec/phycore_am68x/Kconfig
index 37912fb4ed3..d82cdaf819b 100644
--- a/board/phytec/phycore_am68x/Kconfig
+++ b/board/phytec/phycore_am68x/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "phycore_am68x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am68x"
@@ -27,7 +27,7 @@ config SYS_BOARD
        default "phycore_am68x"
 
 config SYS_VENDOR
-       default "phytec"
+	default "phytec"
 
 config SYS_CONFIG_NAME
        default "phycore_am68x"
diff --git a/board/phytec/phycore_am68x/rm-cfg.yaml b/board/phytec/phycore_am68x/rm-cfg.yaml
index 8796463129d..728bfe241a4 100644
--- a/board/phytec/phycore_am68x/rm-cfg.yaml
+++ b/board/phytec/phycore_am68x/rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J721S2
 #
@@ -429,24 +429,24 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 10
-            num_resource: 100
+            num_resource: 98
             type: 14528
             host_id: 12
             reserved: 0
         -
-            start_resource: 110
+            start_resource: 108
             num_resource: 32
             type: 14528
             host_id: 13
             reserved: 0
         -
-            start_resource: 142
+            start_resource: 140
             num_resource: 21
             type: 14528
             host_id: 21
             reserved: 0
         -
-            start_resource: 163
+            start_resource: 161
             num_resource: 21
             type: 14528
             host_id: 23
@@ -1431,7 +1431,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 236
-            num_resource: 20
+            num_resource: 18
             type: 16970
             host_id: 128
             reserved: 0
@@ -1497,7 +1497,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 3426
-            num_resource: 1182
+            num_resource: 1180
             type: 16973
             host_id: 128
             reserved: 0
diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c
index 9fc63febdac..a738e3542e2 100644
--- a/board/phytium/durian/durian.c
+++ b/board/phytium/durian/durian.c
@@ -31,8 +31,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size =  PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c
index 6824454cdf4..421e193e730 100644
--- a/board/phytium/pe2201/pe2201.c
+++ b/board/phytium/pe2201/pe2201.c
@@ -44,8 +44,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS
index 09e7f20e33c..818e1850302 100644
--- a/board/purism/librem5/MAINTAINERS
+++ b/board/purism/librem5/MAINTAINERS
@@ -2,7 +2,6 @@ PURISM LIBREM5 PHONE
 M:	Angus Ainslie <angus@akkea.ca>
 R:	kernel@puri.sm
 S:	Supported
-F:	arch/arm/dts/imx8mq-librem5*
 F:	board/purism/librem5/
 F:	configs/librem5_defconfig
 F:	include/configs/librem5.h
diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config
index d24094eefdd..1387aa1dfa2 100644
--- a/board/qualcomm/qcom-phone.config
+++ b/board/qualcomm/qcom-phone.config
@@ -13,6 +13,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x1A000000
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_USB_FUNCTION_ACM=y
 CONFIG_CMD_UMS_ABORT_KEYED=y
+CONFIG_CMD_FASTBOOT_ABORT_KEYED=y
 
 # Record all console output and let it be dumped via fastboot
 CONFIG_CONSOLE_RECORD=y
diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env
index d1c586bd3fb..5eaa2ceada8 100644
--- a/board/qualcomm/qcom-phone.env
+++ b/board/qualcomm/qcom-phone.env
@@ -32,7 +32,7 @@ menucmd=setenv bootcmd run menucmd; bootmenu -1
 bootmenu_0=Boot=bootefi bootmgr; pause
 bootmenu_1=Enable serial console gadget=run serial_gadget
 bootmenu_2=Enable USB mass storage=echo "Press any key to exit UMS mode"; ums 0 scsi 0
-bootmenu_3=Enable fastboot mode=run fastboot
+bootmenu_3=Enable fastboot mode=echo "Press any key to exit fastboot mode"; run fastboot
 # Disabling bootretry means we'll just drop the shell
 bootmenu_4=Drop to shell=setenv bootretry -1
 bootmenu_5=Reset device=reset
@@ -40,6 +40,7 @@ bootmenu_6=Dump clocks=clk dump; pause
 bootmenu_7=Dump environment=printenv; pause
 bootmenu_8=Board info=bdinfo; pause
 bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause
+bootmenu_10=Power off=poweroff
 
 # Allow holding the volume down button while U-Boot loads to enter
 # the boot menu
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index b0a1484c0fa..1da5df92351 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 unsigned long __section(".data") fw_dtb_pointer;
 
+static phys_addr_t discovered_ram_size;
+
 /* TODO(sjg@chromium.org): Move these to the msg.c file */
 struct msg_get_arm_mem {
 	struct bcm2835_mbox_hdr hdr;
@@ -335,10 +337,16 @@ int dram_init(void)
 	 * the u-boot's memory setup.
 	 */
 	gd->ram_size &= ~MMU_SECTION_SIZE;
+	discovered_ram_size = gd->ram_size;
 
 	return 0;
 }
 
+phys_size_t get_effective_memsize(void)
+{
+	return discovered_ram_size;
+}
+
 #ifdef CONFIG_OF_BOARD
 int dram_init_banksize(void)
 {
@@ -356,9 +364,9 @@ int dram_init_banksize(void)
 
 	/* Update gd->ram_size to reflect total RAM across all banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		if (gd->bd->bi_dram[i].size == 0)
+		if (gd->dram[i].size == 0)
 			break;
-		total_size += gd->bd->bi_dram[i].size;
+		total_size += gd->dram[i].size;
 	}
 	gd->ram_size = total_size;
 
diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c
index 3d537be4d02..09667d46d99 100644
--- a/board/renesas/common/rcar64-common.c
+++ b/board/renesas/common/rcar64-common.c
@@ -49,15 +49,15 @@ int dram_init_banksize(void)
 		return 0;
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		if (gd->bd->bi_dram[bank].start != 0x48000000)
+		if (gd->dram[bank].start != 0x48000000)
 			continue;
 
 		/*
 		 * If this U-Boot runs in EL3, make the bottom 128 MiB
 		 * available for loading of follow up firmware blobs.
 		 */
-		gd->bd->bi_dram[bank].start -= 0x8000000;
-		gd->bd->bi_dram[bank].size += 0x8000000;
+		gd->dram[bank].start -= 0x8000000;
+		gd->dram[bank].size += 0x8000000;
 		break;
 	}
 
diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c
index 8153aed15e3..9245bf348f8 100644
--- a/board/renesas/genmai/genmai.c
+++ b/board/renesas/genmai/genmai.c
@@ -43,7 +43,7 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = gd->ram_base;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = gd->ram_base;
+	gd->dram[0].size = gd->ram_size;
 	return 0;
 }
diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c
index a229542ba7e..1503de675d5 100644
--- a/board/renesas/sparrowhawk/sparrowhawk.c
+++ b/board/renesas/sparrowhawk/sparrowhawk.c
@@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void)
 
 	/* 16 GiB device, adjust memory map. */
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		if (gd->bd->bi_dram[bank].start == 0x480000000ULL)
-			gd->bd->bi_dram[bank].size = 0x180000000ULL;
-		else if (gd->bd->bi_dram[bank].start == 0x600000000ULL)
-			gd->bd->bi_dram[bank].size = 0x200000000ULL;
+		if (gd->dram[bank].start == 0x480000000ULL)
+			gd->dram[bank].size = 0x180000000ULL;
+		else if (gd->dram[bank].start == 0x600000000ULL)
+			gd->dram[bank].size = 0x200000000ULL;
 	}
 }
 
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 1f78654b685..7a0a93c1afe 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -103,8 +103,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->dram[0].start = PHYS_SDRAM;
+	gd->dram[0].size = PHYS_SDRAM_SIZE;
 
 	return 0;
 }
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index cc58e0f3a38..0ff49dceb9e 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -97,8 +97,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->dram[0].start = PHYS_SDRAM;
+	gd->dram[0].size = PHYS_SDRAM_SIZE;
 
 	return 0;
 }
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 5d5edd9f253..b5664296a81 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -150,8 +150,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
 
 	return 0;
 }
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index e70b4a82687..130136e8596 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -67,8 +67,8 @@ int dram_init_banksize(void)
 		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 
-		gd->bd->bi_dram[i].start = addr;
-		gd->bd->bi_dram[i].size = size;
+		gd->dram[i].start = addr;
+		gd->dram[i].size = size;
 	}
 
 	return 0;
diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
index 64a4ffa7e67..d98da0ecab5 100644
--- a/board/samsung/axy17lte/Kconfig
+++ b/board/samsung/axy17lte/Kconfig
@@ -11,8 +11,8 @@ config SYS_CONFIG_NAME
 	default "exynos78x0-common"
 
 config EXYNOS7880
-    bool "Exynos 7880 SOC support"
-    default y
+	bool "Exynos 7880 SOC support"
+	default y
 endif
 
 if TARGET_A7Y17LTE
@@ -28,8 +28,8 @@ config SYS_CONFIG_NAME
 	default "exynos78x0-common"
 
 config EXYNOS7880
-    bool "Exynos 7880 SOC support"
-    default y
+	bool "Exynos 7880 SOC support"
+	default y
 endif
 
 if TARGET_A3Y17LTE
@@ -45,6 +45,6 @@ config SYS_CONFIG_NAME
 	default "exynos78x0-common"
 
 config EXYNOS7870
-    bool "Exynos 7870 SOC support"
-    default y
+	bool "Exynos 7870 SOC support"
+	default y
 endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index eed1c2450fa..da3510023c4 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -115,7 +115,7 @@ int board_init(void)
 	ulong size = CONFIG_SYS_MEM_TOP_HIDE;
 
 	gd->ram_size -= size;
-	gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
+	gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
 #endif
 	exynos_init();
 
@@ -143,8 +143,8 @@ int dram_init_banksize(void)
 		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 
-		gd->bd->bi_dram[i].start = addr;
-		gd->bd->bi_dram[i].size = size;
+		gd->dram[i].start = addr;
+		gd->dram[i].size = size;
 	}
 
 	return 0;
diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c
index 6b2b1523663..d91e2e7d3f2 100644
--- a/board/samsung/exynos-mobile/exynos-mobile.c
+++ b/board/samsung/exynos-mobile/exynos-mobile.c
@@ -346,8 +346,8 @@ int dram_init_banksize(void)
 	unsigned int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = mem_map[i + 1].phys;
-		gd->bd->bi_dram[i].size = mem_map[i + 1].size;
+		gd->dram[i].start = mem_map[i + 1].phys;
+		gd->dram[i].size = mem_map[i + 1].size;
 	}
 
 	return 0;
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index a1047f3fd2a..96a411233d1 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -43,12 +43,12 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->dram[2].start = PHYS_SDRAM_3;
+	gd->dram[2].size = PHYS_SDRAM_3_SIZE;
 
 	return 0;
 }
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 7d0b0fcb0ae..7e992c23a1b 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -56,8 +56,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index 5a4874b29cd..f013893b465 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -57,17 +57,17 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 							PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 							PHYS_SDRAM_2_SIZE);
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
+	gd->dram[2].start = PHYS_SDRAM_3;
+	gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 							PHYS_SDRAM_3_SIZE);
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
+	gd->dram[3].start = PHYS_SDRAM_4;
+	gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 							PHYS_SDRAM_4_SIZE);
 
 	return 0;
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 9d45c4239be..3f2e75b03fe 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -33,10 +33,10 @@ endif
 if TARGET_ETAMIN
 
 config SYS_BOARD
-        default "draco"
+	default "draco"
 
 config SYS_VENDOR
-        default "siemens"
+	default "siemens"
 
 config SYS_SOC
         default "am33xx"
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index 79cf34b40eb..69d3b9d61d3 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -397,20 +397,20 @@ int dram_init_banksize(void)
 
 	if (gd->ram_size > SZ_2G) {
 		/* Bank 0 declares the memory available in the DDR low region */
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = SZ_2G;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = SZ_2G;
 
 		/* Bank 1 declares the memory available in the DDR high region */
-		gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
-		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+		gd->dram[1].start = CFG_SYS_SDRAM_BASE1;
+		gd->dram[1].size = gd->ram_size - SZ_2G;
 	} else {
 		/* Bank 0 declares the memory available in the DDR low region */
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = gd->ram_size;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = gd->ram_size;
 
 		/* Bank 1 declares the memory available in the DDR high region */
-		gd->bd->bi_dram[1].start = 0;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[1].start = 0;
+		gd->dram[1].size = 0;
 	}
 
 	return 0;
diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig
index c181d26a44a..1b1c9181bad 100644
--- a/board/socionext/developerbox/Kconfig
+++ b/board/socionext/developerbox/Kconfig
@@ -11,10 +11,10 @@ config TARGET_DEVELOPERBOX
 	select SYS_DISABLE_DCACHE_OPS
 	select OF_BOARD_SETUP
 	help
-	 Choose this option if you build the U-Boot for the DeveloperBox
-	 96boards Enterprise Edition.
-	 This board will booted from SCP firmware and it enables SMMU, thus
-	 the dcache is updated automatically when DMA operation is executed.
+	  Choose this option if you build the U-Boot for the DeveloperBox
+	  96boards Enterprise Edition.
+	  This board will booted from SCP firmware and it enables SMMU, thus
+	  the dcache is updated automatically when DMA operation is executed.
 endchoice
 
 config SYS_SOC
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index 556a9ed527e..a7bd08f69ad 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -170,11 +170,11 @@ int dram_init_banksize(void)
 	struct draminfo_entry *ent = synquacer_draminfo->entry;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+	for (i = 0; i < ARRAY_SIZE(gd->dram); i++) {
 		if (i < synquacer_draminfo->nr_regions) {
 			debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
-			gd->bd->bi_dram[i].start = ent[i].base;
-			gd->bd->bi_dram[i].size = ent[i].size;
+			gd->dram[i].start = ent[i].base;
+			gd->dram[i].size = ent[i].size;
 		}
 	}
 
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index b8e6e2cd76e..fc0c04efdd1 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -135,7 +135,7 @@ static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ct
 			break;
 
 		default:
-			printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+			printf("%s: unknown ctrl %#x\n", __func__, ctrl);
 		}
 
 		if (ctrl & NAND_NCE)
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index f5174720434..a1b0265d5ac 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -18,8 +18,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	return 0;
 }
diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c
index 826c002907d..66330184af8 100644
--- a/board/ste/stemmy/stemmy.c
+++ b/board/ste/stemmy/stemmy.c
@@ -70,8 +70,8 @@ int dram_init_banksize(void)
 		if (t->hdr.tag != ATAG_MEM)
 			continue;
 
-		gd->bd->bi_dram[bank].start = t->u.mem.start;
-		gd->bd->bi_dram[bank].size = t->u.mem.size;
+		gd->dram[bank].start = t->u.mem.start;
+		gd->dram[bank].size = t->u.mem.size;
 		if (++bank == CONFIG_NR_DRAM_BANKS)
 			break;
 	}
diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig
index b5c81dda237..7efd857dc32 100644
--- a/board/sysam/amcore/Kconfig
+++ b/board/sysam/amcore/Kconfig
@@ -4,13 +4,13 @@ config SYS_CPU
         default "mcf530x"
 
 config SYS_BOARD
-        default "amcore"
+	default "amcore"
 
 config SYS_VENDOR
-        default "sysam"
+	default "sysam"
 
 config SYS_CONFIG_NAME
-        default "amcore"
+	default "amcore"
 
 endif
 
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b5f69a45a7c..4a2d7655d2a 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -28,6 +28,7 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/emif.h>
@@ -72,6 +73,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
 #define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
 
+static __maybe_unused struct module_pin_mux rmii1_mdio_pin_mux[] = {
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{-1},
+};
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -779,6 +786,9 @@ int board_init(void)
 			hang();
 		}
 
+		if (!eth0_is_mii)
+			configure_module_pin_mux(rmii1_mdio_pin_mux);
+
 		prueth_is_mii = eth0_is_mii;
 
 		/* disable rising edge IRQs */
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index d2d87c304f6..36d849d2119 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -190,8 +190,6 @@ static struct module_pin_mux mii1_pin_mux[] = {
 };
 
 static struct module_pin_mux rmii1_pin_mux[] = {
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
 	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
 	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
 	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */
diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig
index 51e7b3e0eab..a80ea9149b1 100644
--- a/board/ti/am62ax/Kconfig
+++ b/board/ti/am62ax/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "am62ax"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am62ax_evm"
diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml
index 4e238883b96..36b0049f43a 100644
--- a/board/ti/am62ax/rm-cfg.yaml
+++ b/board/ti/am62ax/rm-cfg.yaml
@@ -244,7 +244,7 @@ rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 1064
+            resasg_entries_size: 1176
             reserved: 0
     resasg_entries:
         -
@@ -705,13 +705,25 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
             type: 1937
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
+            type: 1937
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
             type: 1937
             host_id: 30
             reserved: 0
@@ -759,13 +771,25 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
             type: 1943
             host_id: 12
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
+            type: 1943
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
             type: 1943
             host_id: 30
             reserved: 0
@@ -825,13 +849,25 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
             type: 1956
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
+            type: 1956
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
             type: 1956
             host_id: 30
             reserved: 0
@@ -917,17 +953,29 @@ rm-cfg:
             start_resource: 19
             num_resource: 1
             type: 1963
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
             type: 1964
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
+            type: 1964
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
             type: 1964
             host_id: 30
             reserved: 0
@@ -1012,22 +1060,58 @@ rm-cfg:
         -
             start_resource: 0
             num_resource: 6
+            type: 12750
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
             type: 12769
             host_id: 12
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 6
+            type: 12769
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 5
             type: 12810
             host_id: 12
             reserved: 0
         -
+            start_resource: 5
+            num_resource: 3
+            type: 12810
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 5
+            num_resource: 3
+            type: 12810
+            host_id: 36
+            reserved: 0
+        -
             start_resource: 12288
-            num_resource: 128
+            num_resource: 64
             type: 12813
             host_id: 12
             reserved: 0
         -
+            start_resource: 12352
+            num_resource: 64
+            type: 12813
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 12352
+            num_resource: 64
+            type: 12813
+            host_id: 36
+            reserved: 0
+        -
             start_resource: 3072
             num_resource: 6
             type: 12828
diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml
index 78bbab38bb6..3706fac8664 100644
--- a/board/ti/am62ax/tifs-rm-cfg.yaml
+++ b/board/ti/am62ax/tifs-rm-cfg.yaml
@@ -244,7 +244,7 @@ tifs-rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 880
+            resasg_entries_size: 976
             reserved: 0
     resasg_entries:
         -
@@ -585,13 +585,25 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
             type: 1937
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
+            type: 1937
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
             type: 1937
             host_id: 30
             reserved: 0
@@ -639,13 +651,25 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
             type: 1943
             host_id: 12
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
+            type: 1943
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
             type: 1943
             host_id: 30
             reserved: 0
@@ -705,13 +729,25 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
             type: 1956
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
+            type: 1956
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
             type: 1956
             host_id: 30
             reserved: 0
@@ -797,17 +833,29 @@ tifs-rm-cfg:
             start_resource: 19
             num_resource: 1
             type: 1963
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
             type: 1964
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
+            type: 1964
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
             type: 1964
             host_id: 30
             reserved: 0
@@ -880,16 +928,40 @@ tifs-rm-cfg:
         -
             start_resource: 0
             num_resource: 6
+            type: 12750
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
             type: 12769
             host_id: 12
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 6
+            type: 12769
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 5
             type: 12810
             host_id: 12
             reserved: 0
         -
+            start_resource: 5
+            num_resource: 3
+            type: 12810
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 5
+            num_resource: 3
+            type: 12810
+            host_id: 36
+            reserved: 0
+        -
             start_resource: 3072
             num_resource: 6
             type: 12828
diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig
index 9d95ffd9b29..1011b89d75f 100644
--- a/board/ti/am62px/Kconfig
+++ b/board/ti/am62px/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "am62px"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am62px_evm"
diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig
index 610dacfdc08..eb54154d1ce 100644
--- a/board/ti/am62x/Kconfig
+++ b/board/ti/am62x/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "am62x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am62x_evm"
@@ -24,7 +24,7 @@ config SYS_BOARD
        default "am62x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am62x_evm"
diff --git a/board/ti/am62x/am6254atl.env b/board/ti/am62x/am6254atl.env
index ea5a33d8cc3..a9187c2b1aa 100644
--- a/board/ti/am62x/am6254atl.env
+++ b/board/ti/am62x/am6254atl.env
@@ -27,10 +27,6 @@ splashimage=0x82180000
 splashpos=m,m
 splashsource=sf
 
-dfu_alt_info_ram=
-	tispl.bin ram 0x82000000 0x200000;
-	u-boot.img ram 0x82f80000 0x400000
-
 #if CONFIG_BOOTMETH_ANDROID
 #include <env/ti/android.env>
 adtb_idx=0
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
index b873476a9d5..c727b7f8c16 100644
--- a/board/ti/am64x/Kconfig
+++ b/board/ti/am64x/Kconfig
@@ -8,7 +8,7 @@ config SYS_BOARD
        default "am64x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am64x_evm"
@@ -23,7 +23,7 @@ config SYS_BOARD
        default "am64x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am64x_evm"
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index eb47a25c70a..fe3fa13dc4b 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "am65x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am65x_evm"
@@ -24,7 +24,7 @@ config SYS_BOARD
        default "am65x"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "am65x_evm"
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index 149909093b3..6762d08d400 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -1,8 +1,8 @@
 config TI_I2C_BOARD_DETECT
 	bool "Support for Board detection for TI platforms"
 	help
-	   Support for detection board information on Texas Instrument's
-	   Evaluation Boards which have I2C based EEPROM detection
+	  Support for detection board information on Texas Instrument's
+	  Evaluation Boards which have I2C based EEPROM detection
 
 config EEPROM_BUS_ADDRESS
 	int "Board EEPROM's I2C bus address"
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 0966db2bb62..6f1fed43e36 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -643,11 +643,11 @@ int dram_init_banksize(void)
 
 	ram_size = board_ti_get_emif_size();
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = get_effective_memsize();
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = get_effective_memsize();
 	if (ram_size > CFG_MAX_MEM_MAPPED) {
-		gd->bd->bi_dram[1].start = 0x200000000;
-		gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
+		gd->dram[1].start = 0x200000000;
+		gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
 	}
 
 	return 0;
diff --git a/board/ti/j7200/Kconfig b/board/ti/j7200/Kconfig
index 093d23e7bf8..38edbe12968 100644
--- a/board/ti/j7200/Kconfig
+++ b/board/ti/j7200/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "j7200"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721e_evm"
@@ -27,7 +27,7 @@ config SYS_BOARD
        default "j7200"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721e_evm"
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 7c7e23988d8..d85056e65bb 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "j721e"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721e_evm"
@@ -27,7 +27,7 @@ config SYS_BOARD
        default "j721e"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721e_evm"
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
index 40853a8fd66..34a3e6ef187 100644
--- a/board/ti/j721s2/Kconfig
+++ b/board/ti/j721s2/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "j721s2"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721s2_evm"
@@ -27,7 +27,7 @@ config SYS_BOARD
        default "j721s2"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j721s2_evm"
diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig
index 68c214e473b..e819ba2f554 100644
--- a/board/ti/j722s/Kconfig
+++ b/board/ti/j722s/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "j722s"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j722s_evm"
diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml
index e9a9d526cfb..b68b305b6bb 100644
--- a/board/ti/j722s/sec-cfg.yaml
+++ b/board/ti/j722s/sec-cfg.yaml
@@ -16,9 +16,9 @@ sec-cfg:
             size: 164
         proc_acl_entries:
             -
-                processor_id: 0
-                proc_access_master: 0
-                proc_access_secondary: [0, 0, 0]
+                processor_id: 0x1
+                proc_access_master: 0x23
+                proc_access_secondary: [0xC, 0, 0]
             -
                 processor_id: 0
                 proc_access_master: 0
diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig
index de95ac575d7..40c4913aea1 100644
--- a/board/ti/j784s4/Kconfig
+++ b/board/ti/j784s4/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "j784s4"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j784s4_evm"
@@ -24,7 +24,7 @@ config SYS_BOARD
        default "j784s4"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j784s4_evm"
@@ -42,7 +42,7 @@ config SYS_BOARD
        default "j784s4"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j784s4_evm"
@@ -57,7 +57,7 @@ config SYS_BOARD
        default "j784s4"
 
 config SYS_VENDOR
-       default "ti"
+	default "ti"
 
 config SYS_CONFIG_NAME
        default "j784s4_evm"
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index a92aa5cfc67..43330993955 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	}
 
 	nbanks = 1;
-	start[0] = bd->bi_dram[0].start;
-	size[0]  = bd->bi_dram[0].size;
+	start[0] = gd->dram[0].start;
+	size[0]  = gd->dram[0].size;
 
 	/* adjust memory start address for LPAE */
 	if (lpae) {
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
index c6ff387351c..fc4cbe3323c 100644
--- a/board/toradex/apalis_imx6/Kconfig
+++ b/board/toradex/apalis_imx6/Kconfig
@@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR
 	bool "Enable factory testing commands for Toradex iMX 6 modules"
 	help
 	  This adds the commands
-	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
 	  If executed on already fused modules it doesn't change any fuse setting.
 	default y
 
@@ -43,11 +43,11 @@ config TDX_APALIS_IMX6_V1_0
 	bool "Apalis iMX6 V1.0 HW"
 	help
 	  Apalis iMX6 V1.0 HW has a different pinout for the UART.
-	    The UARTs must be used in DCE mode, RTS/CTS are swapped and
-	    thus unusable on standard carrier boards.
-	    This option configures DCE mode unconditionally. Whithout this
-	    option the config block stating V1.0 HW selects DCE mode,
-	    otherwise the UARTs are configuered in DTE mode.
+	  The UARTs must be used in DCE mode, RTS/CTS are swapped and
+	  thus unusable on standard carrier boards.
+	  This option configures DCE mode unconditionally. Whithout this
+	  option the config block stating V1.0 HW selects DCE mode,
+	  otherwise the UARTs are configuered in DTE mode.
 
 source "board/toradex/common/Kconfig"
 
diff --git a/board/toradex/aquila-am69/Kconfig b/board/toradex/aquila-am69/Kconfig
index 6afa97e2c82..b44b9247603 100644
--- a/board/toradex/aquila-am69/Kconfig
+++ b/board/toradex/aquila-am69/Kconfig
@@ -9,7 +9,7 @@ config SYS_BOARD
        default "aquila-am69"
 
 config SYS_VENDOR
-       default "toradex"
+	default "toradex"
 
 config SYS_CONFIG_NAME
        default "aquila-am69"
@@ -48,7 +48,7 @@ config SYS_BOARD
        default "aquila-am69"
 
 config SYS_VENDOR
-       default "toradex"
+	default "toradex"
 
 config SYS_CONFIG_NAME
        default "aquila-am69"
diff --git a/board/toradex/aquila-am69/rm-cfg.yaml b/board/toradex/aquila-am69/rm-cfg.yaml
index 02a753a0a9f..a3cf5643dc5 100644
--- a/board/toradex/aquila-am69/rm-cfg.yaml
+++ b/board/toradex/aquila-am69/rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J784S4
 #
@@ -453,36 +453,36 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 16
-            num_resource: 80
+            num_resource: 78
             type: 18112
             host_id: 12
             reserved: 0
         -
-            start_resource: 96
+            start_resource: 94
             num_resource: 14
             type: 18112
             host_id: 13
             reserved: 0
         -
-            start_resource: 110
+            start_resource: 108
             num_resource: 21
             type: 18112
             host_id: 21
             reserved: 0
         -
-            start_resource: 131
+            start_resource: 129
             num_resource: 21
             type: 18112
             host_id: 23
             reserved: 0
         -
-            start_resource: 152
+            start_resource: 150
             num_resource: 12
             type: 18112
             host_id: 25
             reserved: 0
         -
-            start_resource: 164
+            start_resource: 162
             num_resource: 12
             type: 18112
             host_id: 27
@@ -1719,72 +1719,72 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 56
-            num_resource: 56
+            num_resource: 54
             type: 20554
             host_id: 12
             reserved: 0
         -
-            start_resource: 112
+            start_resource: 110
             num_resource: 24
             type: 20554
             host_id: 13
             reserved: 0
         -
-            start_resource: 136
+            start_resource: 134
             num_resource: 12
             type: 20554
             host_id: 21
             reserved: 0
         -
-            start_resource: 148
+            start_resource: 146
             num_resource: 12
             type: 20554
             host_id: 23
             reserved: 0
         -
-            start_resource: 160
+            start_resource: 158
             num_resource: 10
             type: 20554
             host_id: 25
             reserved: 0
         -
-            start_resource: 170
+            start_resource: 168
             num_resource: 10
             type: 20554
             host_id: 27
             reserved: 0
         -
-            start_resource: 180
+            start_resource: 178
             num_resource: 28
             type: 20554
             host_id: 35
             reserved: 0
         -
-            start_resource: 208
+            start_resource: 206
             num_resource: 8
             type: 20554
             host_id: 37
             reserved: 0
         -
-            start_resource: 216
+            start_resource: 214
             num_resource: 12
             type: 20554
             host_id: 40
             reserved: 0
         -
-            start_resource: 228
+            start_resource: 226
             num_resource: 8
             type: 20554
             host_id: 42
             reserved: 0
         -
-            start_resource: 236
+            start_resource: 234
             num_resource: 10
             type: 20554
             host_id: 45
             reserved: 0
         -
-            start_resource: 246
+            start_resource: 244
             num_resource: 10
             type: 20554
             host_id: 47
@@ -1875,7 +1875,7 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 4472
-            num_resource: 136
+            num_resource: 134
             type: 20557
             host_id: 128
             reserved: 0
diff --git a/board/toradex/aquila-am69/tifs-rm-cfg.yaml b/board/toradex/aquila-am69/tifs-rm-cfg.yaml
index 2889baacf82..964d9e47e66 100644
--- a/board/toradex/aquila-am69/tifs-rm-cfg.yaml
+++ b/board/toradex/aquila-am69/tifs-rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for J784S4
 #
@@ -1455,72 +1455,72 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 56
-            num_resource: 56
+            num_resource: 54
             type: 20554
             host_id: 12
             reserved: 0
         -
-            start_resource: 112
+            start_resource: 110
             num_resource: 24
             type: 20554
             host_id: 13
             reserved: 0
         -
-            start_resource: 136
+            start_resource: 134
             num_resource: 12
             type: 20554
             host_id: 21
             reserved: 0
         -
-            start_resource: 148
+            start_resource: 146
             num_resource: 12
             type: 20554
             host_id: 23
             reserved: 0
         -
-            start_resource: 160
+            start_resource: 158
             num_resource: 10
             type: 20554
             host_id: 25
             reserved: 0
         -
-            start_resource: 170
+            start_resource: 168
             num_resource: 10
             type: 20554
             host_id: 27
             reserved: 0
         -
-            start_resource: 180
+            start_resource: 178
             num_resource: 28
             type: 20554
             host_id: 35
             reserved: 0
         -
-            start_resource: 208
+            start_resource: 206
             num_resource: 8
             type: 20554
             host_id: 37
             reserved: 0
         -
-            start_resource: 216
+            start_resource: 214
             num_resource: 12
             type: 20554
             host_id: 40
             reserved: 0
         -
-            start_resource: 228
+            start_resource: 226
             num_resource: 8
             type: 20554
             host_id: 42
             reserved: 0
         -
-            start_resource: 236
+            start_resource: 234
             num_resource: 10
             type: 20554
             host_id: 45
             reserved: 0
         -
-            start_resource: 246
+            start_resource: 244
             num_resource: 10
             type: 20554
             host_id: 47
diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig
new file mode 100644
index 00000000000..5936946e1af
--- /dev/null
+++ b/board/toradex/aquila-imx95/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_AQUILA_IMX95
+
+config SYS_BOARD
+	default "aquila-imx95"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "aquila-imx95"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS
new file mode 100644
index 00000000000..d2a74a53f5e
--- /dev/null
+++ b/board/toradex/aquila-imx95/MAINTAINERS
@@ -0,0 +1,11 @@
+Aquila iMX95
+F:	arch/arm/dts/imx95-aquila.dtsi
+F:	arch/arm/dts/imx95-aquila-dev.dts
+F:	arch/arm/dts/imx95-aquila-dev-u-boot.dtsi
+F:	board/toradex/aquila-imx95/
+F:	configs/aquila-imx95_defconfig
+F:	doc/board/toradex/aquila-imx95.rst
+F:	include/configs/aquila-imx95.h
+M:	Francesco Dolcini <francesco.dolcini@toradex.com>
+S:	Maintained
+W:	https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile
new file mode 100644
index 00000000000..caaf09465c8
--- /dev/null
+++ b/board/toradex/aquila-imx95/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (c) Toradex
+
+obj-y += aquila-imx95.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c
new file mode 100644
index 00000000000..0c6473e4b3a
--- /dev/null
+++ b/board/toradex/aquila-imx95/aquila-imx95.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (c) Toradex */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <fdt_support.h>
+#include <init.h>
+
+#include "../common/tdx-cfg-block.h"
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	*size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env
new file mode 100644
index 00000000000..5ca6cb18aaa
--- /dev/null
+++ b/board/toradex/aquila-imx95/aquila-imx95.env
@@ -0,0 +1,20 @@
+boot_scripts=boot.scr
+boot_script_dhcp=boot.scr
+boot_targets=mmc1 mmc0 dhcp
+console=ttyLP2
+fdt_board=dev
+fdt_addr=0x9c400000
+fdt_addr_r=0x9c400000
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0x94400000
+kernel_comp_size=0x8000000
+ramdisk_addr_r=0x9c800000
+scriptaddr=0x9c600000
+
+update_uboot=
+		askenv confirm Did you load flash.bin (y/N)?;
+		if test "$confirm" = y; then
+			setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt
+			${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0
+			${blkcnt};
+		fi
diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c
new file mode 100644
index 00000000000..9f501c11c1d
--- /dev/null
+++ b/board/toradex/aquila-imx95/spl.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (c) Toradex */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/sections.h>
+#include <asm/global_data.h>
+#include <clk.h>
+#include <dm/uclass.h>
+#include <hang.h>
+#include <i2c.h>
+#include <init.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = ele_start_rng();
+	if (ret)
+		printf("Fail to start RNG: %d\n", ret);
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION))
+		spl_save_restore_data();
+
+	timer_init();
+
+	/* Need dm_init() to run before any SCMI calls */
+	spl_early_init();
+
+	/* Need to enable SCMI drivers and ELE driver before console */
+	ret = imx9_probe_mu();
+	if (ret)
+		hang(); /* MU not probed, nothing can be outputed, hang */
+
+	arch_cpu_init();
+
+	preloader_console_init();
+
+	debug("SOC: 0x%x\n", gd->arch.soc_rev);
+	debug("LC: 0x%x\n", gd->arch.lifecycle);
+
+	get_reset_reason(true, false);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig
index d2ad1ce2a03..53d3469d439 100644
--- a/board/toradex/colibri_imx6/Kconfig
+++ b/board/toradex/colibri_imx6/Kconfig
@@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR
 	bool "Enable factory testing commands for Toradex iMX 6 modules"
 	help
 	  This adds the commands
-	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
 	  If executed on already fused modules it doesn't change any fuse setting.
 	default y
 
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 69a8a18d3a7..c63812bd966 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 		 * Reserve 1MB of memory for M4 (1MiB is also the minimum
 		 * alignment for Linux due to MMU section size restrictions).
 		 */
-		start[0] = gd->bd->bi_dram[0].start;
+		start[0] = gd->dram[0].start;
 		size[0] = SZ_256M - SZ_1M;
 
 		/* If needed, create a second entry for memory beyond 256M */
-		if (gd->bd->bi_dram[0].size > SZ_256M) {
-			start[1] = gd->bd->bi_dram[0].start + SZ_256M;
-			size[1] = gd->bd->bi_dram[0].size - SZ_256M;
+		if (gd->dram[0].size > SZ_256M) {
+			start[1] = gd->dram[0].start + SZ_256M;
+			size[1] = gd->dram[0].size - SZ_256M;
 			areas = 2;
 		}
 
diff --git a/board/toradex/verdin-am62/tifs-rm-cfg.yaml b/board/toradex/verdin-am62/tifs-rm-cfg.yaml
new file mode 100644
index 00000000000..8510fe9526e
--- /dev/null
+++ b/board/toradex/verdin-am62/tifs-rm-cfg.yaml
@@ -0,0 +1,867 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62X
+#
+
+---
+
+tifs-rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                -  # 1
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 2
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 3
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 4
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 5
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 6
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 7
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 8
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 9
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 10
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 11
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 12
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 13
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 14
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 15
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 16
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 17
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 18
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 19
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 20
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 21
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 22
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 23
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 24
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 25
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 26
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 27
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 28
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 29
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 30
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 31
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 32
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 824
+            reserved: 0
+    resasg_entries:
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1677
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1677
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 6
+            type: 1677
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 54
+            num_resource: 18
+            type: 1678
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 72
+            num_resource: 6
+            type: 1678
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 72
+            num_resource: 6
+            type: 1678
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 78
+            num_resource: 2
+            type: 1678
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 80
+            num_resource: 2
+            type: 1678
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 32
+            num_resource: 12
+            type: 1679
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 6
+            type: 1679
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 6
+            type: 1679
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 50
+            num_resource: 2
+            type: 1679
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 52
+            num_resource: 2
+            type: 1679
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1696
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1696
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 6
+            type: 1696
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1697
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1697
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 2
+            type: 1697
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 12
+            type: 1698
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 2
+            type: 1698
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 2
+            type: 1698
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5
+            num_resource: 35
+            type: 1802
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 168
+            num_resource: 7
+            type: 1802
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1024
+            type: 1807
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 29
+            type: 1808
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4608
+            num_resource: 99
+            type: 1809
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5120
+            num_resource: 24
+            type: 1810
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5632
+            num_resource: 51
+            type: 1811
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6144
+            num_resource: 51
+            type: 1812
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6656
+            num_resource: 51
+            type: 1813
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8192
+            num_resource: 32
+            type: 1814
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8704
+            num_resource: 32
+            type: 1815
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9216
+            num_resource: 32
+            type: 1816
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9728
+            num_resource: 22
+            type: 1817
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10240
+            num_resource: 22
+            type: 1818
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10752
+            num_resource: 22
+            type: 1819
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11264
+            num_resource: 28
+            type: 1820
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11776
+            num_resource: 28
+            type: 1821
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 12288
+            num_resource: 28
+            type: 1822
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1936
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1936
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1936
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 83
+            num_resource: 8
+            type: 1938
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 91
+            num_resource: 8
+            type: 1939
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 99
+            num_resource: 10
+            type: 1942
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 112
+            num_resource: 3
+            type: 1942
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 115
+            num_resource: 3
+            type: 1942
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1944
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1945
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1946
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1947
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1955
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1955
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1955
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 27
+            num_resource: 1
+            type: 1957
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 1
+            type: 1958
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1961
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1961
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1961
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1962
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1962
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1962
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 1
+            type: 1965
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1966
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 21
+            num_resource: 1
+            type: 1967
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1968
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 1
+            type: 1969
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1970
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 1
+            type: 1971
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1972
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 2112
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 2
+            type: 2122
+            host_id: 12
+            reserved: 0
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index 19ac2ae9313..26af1af2069 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -44,7 +44,7 @@ int dram_init_banksize(void)
 		printf("Error setting up memory banksize. %d\n", ret);
 
 	/* Use the detected RAM size, we only support 1 bank right now. */
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].size = gd->ram_size;
 
 	return ret;
 }
diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig
index a65caf3c26d..4f5968bca2e 100644
--- a/board/toradex/verdin-am62p/Kconfig
+++ b/board/toradex/verdin-am62p/Kconfig
@@ -8,22 +8,22 @@ choice
 	optional
 
 config TARGET_VERDIN_AM62P_A53
-        bool "Toradex Verdin AM62P running on A53"
-        select ARM64
-        select BINMAN
-        select OF_SYSTEM_SETUP
-        imply OF_UPSTREAM
+	bool "Toradex Verdin AM62P running on A53"
+	select ARM64
+	select BINMAN
+	select OF_SYSTEM_SETUP
+	imply OF_UPSTREAM
 
 config TARGET_VERDIN_AM62P_R5
-        bool "Toradex Verdin AM62P running on R5"
-        select CPU_V7R
-        select SYS_THUMB_BUILD
-        select K3_LOAD_SYSFW
-        select RAM
-        select SPL_RAM
-        select K3_DDRSS
-        select BINMAN
-        imply SYS_K3_SPL_ATF
+	bool "Toradex Verdin AM62P running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
 
 endchoice
 
diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml
index 80269748057..73efceafc75 100644
--- a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml
+++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for AM62P
 #
@@ -9,231 +9,231 @@
 tifs-rm-cfg:
     rm_boardcfg:
         rev:
-            boardcfg_abi_maj : 0x0
-            boardcfg_abi_min : 0x1
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
         host_cfg:
             subhdr:
                 magic: 0x4C41
-                size : 356
+                size: 356
             host_cfg_entries:
-                - #1
+                -  # 1
                     host_id: 12
                     allowed_atype: 0x2A
                     allowed_qos: 0xAAAA
                     allowed_orderid: 0xAAAAAAAA
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
-                - #2
+                -  # 2
                     host_id: 30
                     allowed_atype: 0x2A
                     allowed_qos: 0xAAAA
                     allowed_orderid: 0xAAAAAAAA
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
-                - #3
+                -  # 3
                     host_id: 36
                     allowed_atype: 0x2A
                     allowed_qos: 0xAAAA
                     allowed_orderid: 0xAAAAAAAA
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
-                - #4
+                -  # 4
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #5
+                -  # 5
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #6
+                -  # 6
                     host_id: 0
                     allowed_atype: 0
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                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #7
+                -  # 7
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #8
+                -  # 8
                     host_id: 0
                     allowed_atype: 0
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                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #9
+                -  # 9
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #10
+                -  # 10
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #11
+                -  # 11
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #12
+                -  # 12
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #13
+                -  # 13
                     host_id: 0
                     allowed_atype: 0
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                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #14
+                -  # 14
                     host_id: 0
                     allowed_atype: 0
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                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #15
+                -  # 15
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #16
+                -  # 16
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #17
+                -  # 17
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #18
+                -  # 18
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #19
+                -  # 19
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #20
+                -  # 20
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #21
+                -  # 21
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #22
+                -  # 22
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #23
+                -  # 23
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #24
+                -  # 24
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #25
+                -  # 25
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #26
+                -  # 26
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #27
+                -  # 27
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #28
+                -  # 28
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #29
+                -  # 29
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #30
+                -  # 30
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #31
+                -  # 31
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
                     allowed_orderid: 0
                     allowed_priority: 0
                     allowed_sched_priority: 0
-                - #32
+                -  # 32
                     host_id: 0
                     allowed_atype: 0
                     allowed_qos: 0
@@ -244,684 +244,732 @@ tifs-rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
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+            resasg_entries_size: 968
             reserved: 0
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+        -
+            start_resource: 44
+            num_resource: 6
+            type: 1679
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 50
+            num_resource: 2
+            type: 1679
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 52
+            num_resource: 5
+            type: 1679
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 2
+            type: 1695
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 3
+            num_resource: 1
+            type: 1695
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4
+            num_resource: 18
+            type: 1696
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 6
+            type: 1696
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 6
+            type: 1696
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 2
+            type: 1696
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 30
+            num_resource: 2
+            type: 1696
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1697
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 5
+            type: 1697
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 5
+            type: 1697
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 2
+            type: 1697
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 12
+            type: 1698
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 2
+            type: 1698
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 5
+            type: 1698
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5
+            num_resource: 35
+            type: 1802
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 35
+            type: 1802
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 168
+            num_resource: 8
+            type: 1802
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 29
+            type: 1807
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4608
+            num_resource: 99
+            type: 1808
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5120
+            num_resource: 24
+            type: 1809
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5632
+            num_resource: 51
+            type: 1810
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6144
+            num_resource: 51
+            type: 1811
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8192
+            num_resource: 32
+            type: 1812
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8704
+            num_resource: 32
+            type: 1813
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9216
+            num_resource: 32
+            type: 1814
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9728
+            num_resource: 25
+            type: 1815
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10240
+            num_resource: 25
+            type: 1816
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10752
+            num_resource: 25
+            type: 1817
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11264
+            num_resource: 25
+            type: 1818
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11776
+            num_resource: 25
+            type: 1819
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 12288
+            num_resource: 25
+            type: 1820
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1936
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1936
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1936
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 32
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 32
+            type: 1937
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 83
+            num_resource: 8
+            type: 1938
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 91
+            num_resource: 8
+            type: 1939
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 99
+            num_resource: 10
+            type: 1942
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 112
+            num_resource: 3
+            type: 1942
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 115
+            num_resource: 3
+            type: 1942
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 6
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 6
+            type: 1943
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1944
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1945
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1946
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1947
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1955
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1955
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1955
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 4
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 4
+            type: 1956
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 27
+            num_resource: 1
+            type: 1957
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 1
+            type: 1958
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1961
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1961
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1961
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1962
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1962
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1962
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 6
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 6
+            type: 1964
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 1
+            type: 1965
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1966
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 21
+            num_resource: 1
+            type: 1967
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1968
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 1
+            type: 1969
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1970
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 1
+            type: 1971
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1972
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 2112
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 2
+            type: 2122
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12750
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12769
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 8
+            type: 12810
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 3072
+            num_resource: 6
+            type: 12826
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 3584
+            num_resource: 6
+            type: 12827
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 6
+            type: 12828
+            host_id: 128
+            reserved: 0
diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c
index 1234b3887c6..ec7775e06a7 100644
--- a/board/toradex/verdin-am62p/verdin-am62p.c
+++ b/board/toradex/verdin-am62p/verdin-am62p.c
@@ -78,7 +78,7 @@ int dram_init_banksize(void)
 		printf("Error setting up memory banksize. %d\n", ret);
 
 	/* Use the detected RAM size, we only support 1 bank right now. */
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].size = gd->ram_size;
 
 	return ret;
 }
diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS
index b31c5793432..a04a36ba415 100644
--- a/board/tq/MAINTAINERS
+++ b/board/tq/MAINTAINERS
@@ -1,4 +1,4 @@
-TQMA6
+TQMA6 / TQMA6UL / TQMA6ULxL / TQMA6ULL / TQMA6ULLxL
 M:	Max Merchel <max.merchel@ew.tq-group.com>
 L:	u-boot@ew.tq-group.com
 S:	Maintained
diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig
index 2fe2ca30072..567b6e2380a 100644
--- a/board/tq/common/Kconfig
+++ b/board/tq/common/Kconfig
@@ -14,3 +14,8 @@ config TQ_COMMON_SDMMC
 
 config TQ_COMMON_SOM
 	bool
+
+config TQ_COMMON_SYSINFO
+	bool
+	select SYSINFO
+	imply SYSINFO_TQ_EEPROM
diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile
index 4af9207da4a..6cb39a1925e 100644
--- a/board/tq/common/Makefile
+++ b/board/tq/common/Makefile
@@ -8,3 +8,4 @@
 obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o
 obj-$(CONFIG_TQ_COMMON_SOM) += tq_som.o
 obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o
+obj-$(CONFIG_$(PHASE_)TQ_COMMON_SYSINFO) += tq_sysinfo.o
diff --git a/board/tq/common/tq_sysinfo.c b/board/tq/common/tq_sysinfo.c
new file mode 100644
index 00000000000..8d21d1e97c6
--- /dev/null
+++ b/board/tq/common/tq_sysinfo.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Common sysinfo helpers for TQ-Systems SOMs
+ *
+ * Copyright (c) 2020-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>
+ * D-82229 Seefeld, Germany.
+ * Author: Nora Schiffer
+ */
+
+#include <env.h>
+#include <log.h>
+#include <sysinfo/tq_eeprom.h>
+
+#include "tq_sysinfo.h"
+
+#define MAX_NAME_LENGTH	80
+
+int tq_common_sysinfo_setup(void)
+{
+	struct udevice *sysinfo;
+	char buf[MAX_NAME_LENGTH];
+	int ret;
+
+	ret = sysinfo_get_and_detect(&sysinfo);
+	if (ret) {
+		log_debug("Failed to get sysinfo data: %d\n", ret);
+		return ret;
+	}
+
+	if (!sysinfo_get_str(sysinfo, SYSID_TQ_MODEL, sizeof(buf), buf))
+		env_set_runtime("boardtype", buf);
+
+	if (!sysinfo_get_str(sysinfo, SYSID_TQ_SERIAL, sizeof(buf), buf))
+		env_set_runtime("serial#", buf);
+
+	return 0;
+}
diff --git a/board/tq/common/tq_sysinfo.h b/board/tq/common/tq_sysinfo.h
new file mode 100644
index 00000000000..d73b00eb8d7
--- /dev/null
+++ b/board/tq/common/tq_sysinfo.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Common sysinfo helpers for TQ-Systems SOMs
+ *
+ * Copyright (c) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>
+ * D-82229 Seefeld, Germany.
+ * Author: Nora Schiffer
+ */
+
+#ifndef __TQ_SYSINFO_H
+#define __TQ_SYSINFO_H
+
+int tq_common_sysinfo_setup(void);
+
+#endif /* __TQ_SYSINFO_H */
diff --git a/board/tq/tqma6ul/Kconfig b/board/tq/tqma6ul/Kconfig
new file mode 100644
index 00000000000..5d85c68b359
--- /dev/null
+++ b/board/tq/tqma6ul/Kconfig
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+# D-82229 Seefeld, Germany.
+# Author: Marco Felsch, Markus Niebel, Max Merchel
+#
+
+if TARGET_TQMA6UL
+
+config SYS_BOARD
+	default "tqma6ul"
+
+config SYS_VENDOR
+	default "tq"
+
+config SYS_CONFIG_NAME
+	default "tqma6ul_mba6ul" if MBA6UL
+
+choice
+	prompt "TQMa6UL module variant"
+	default TQMA6UL_VARIANT_STANDARD
+	help
+	  Select the variant of the TQMa6UL SoM module being used.
+	  By default, the variant with board-to-board connectors is used.
+
+config TQMA6UL_VARIANT_STANDARD
+	bool "standard module with board connector"
+	help
+	  Select for SoM variant connector
+	  with board to board connectors
+
+config TQMA6UL_VARIANT_LGA
+	bool "LGA module with solder balls"
+	help
+	  Select for SoM variant LGA
+	  with solder balls
+
+endchoice
+
+config TQMA6UL_RAM_256M
+	bool
+
+config TQMA6UL_RAM_512M
+	bool
+
+choice
+	prompt "TQMa6UL RAM configuration"
+	default TQMA6UL_RAM_MULTI
+	help
+	  Select RAM configuration. Normally use default here but for
+	  specific setup it is possible to use a single RAM size.
+
+config TQMA6UL_RAM_MULTI
+	bool "TQMa6ULx with 256/512 MB RAM - Single image"
+	select TQMA6UL_RAM_256M
+	select TQMA6UL_RAM_512M
+	help
+	  Build a single U-Boot solely for variants
+	  with 256/512 MB RAM.
+
+config TQMA6UL_RAM_SINGLE_256M
+	bool "TQMa6UL with 256 MB RAM"
+	select TQMA6UL_RAM_256M
+	help
+	  Build U-Boot solely for variants
+	  with 256 MB RAM.
+
+config TQMA6UL_RAM_SINGLE_512M
+	bool "TQMa6UL with 512 MB RAM"
+	select TQMA6UL_RAM_512M
+	help
+	  Build U-Boot solely for variants
+	  with 512 MB RAM.
+
+endchoice
+
+choice
+	prompt "TQMa6UL base board variant"
+	default MBA6UL
+	help
+	  Select the baseboard variant for the TQMa6UL module.
+	  By default the MBA6UL starterkit is used.
+
+config MBA6UL
+	bool "TQMa6UL on MBa6ULx Starterkit"
+	select TQ_COMMON_BB
+	select TQ_COMMON_SDMMC
+	select SYSINFO
+	select SYSINFO_TQ_EEPROM
+	select I2C_EEPROM
+	select MISC
+	select MXC_UART
+	imply DM_ETH
+	imply DM_GPIO
+	imply DM_MMC
+	imply DM_SERIAL
+	imply DM_SPI
+	imply OF_UPSTREAM
+	imply PHYLIB
+	imply PHY_SMSC
+	imply USB
+	imply USB_STORAGE
+	help
+	  Select the MBa6ULx starterkit.
+	  This is the default base board.
+
+endchoice
+
+config IMX_CONFIG
+	default "board/tq/tqma6ul/tqma6ul.cfg"
+
+source "board/tq/common/Kconfig"
+
+endif
diff --git a/board/tq/tqma6ul/Makefile b/board/tq/tqma6ul/Makefile
new file mode 100644
index 00000000000..f45ed4a15f6
--- /dev/null
+++ b/board/tq/tqma6ul/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2021-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+# D-82229 Seefeld, Germany.
+# Author: Markus Niebel, Matthias Schiffer, Max Merchel
+#
+
+obj-y  := tqma6ul.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += spl_tqma6ul_ram.o
+obj-$(CONFIG_MBA6UL) += spl_mba6ul.o
+else
+obj-$(CONFIG_MBA6UL) += tqma6ul_mba6ul.o
+endif
diff --git a/board/tq/tqma6ul/spl.c b/board/tq/tqma6ul/spl.c
new file mode 100644
index 00000000000..71c5134c4f6
--- /dev/null
+++ b/board/tq/tqma6ul/spl.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ */
+
+#include <fsl_esdhc_imx.h>
+#include <hang.h>
+#include <init.h>
+#include <mmc.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/sections.h>
+#include <linux/sizes.h>
+
+#include "../common/tq_bb.h"
+#include "../common/tq_som.h"
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+/* eMMC on USDHC2 */
+static const iomux_v3_cfg_t tqma6ul_usdhc2_pads[] = {
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg tqma6ul_usdhc2_cfg = {
+	.esdhc_base = USDHC2_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		/* eMMC/uSDHC2 is always present */
+		ret = 1;
+	else
+		ret = tq_bb_board_mmc_getcd(mmc);
+
+	return ret;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		/* eMMC/uSDHC2 is never WP */
+		ret = 0;
+	else
+		ret = tq_bb_board_mmc_getwp(mmc);
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(tqma6ul_usdhc2_pads,
+					 ARRAY_SIZE(tqma6ul_usdhc2_pads));
+	tqma6ul_usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	if (fsl_esdhc_initialize(bis, &tqma6ul_usdhc2_cfg))
+		printf("Warning: failed to initialize eMMC dev\n");
+
+	tq_bb_board_mmc_init(bis);
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup AXI */
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	tq_som_ram_init();
+}
diff --git a/board/tq/tqma6ul/spl_mba6ul.c b/board/tq/tqma6ul/spl_mba6ul.c
new file mode 100644
index 00000000000..55beeac8fc9
--- /dev/null
+++ b/board/tq/tqma6ul/spl_mba6ul.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ */
+
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <malloc.h>
+#include <spl.h>
+#include <spl_gpio.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/mach-imx/sys_proto.h>
+
+#include "../common/tq_bb.h"
+#include "tqma6ul.h"
+
+#define GPIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+		       PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
+			    PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
+			    PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t mba6ul_uart_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL),
+};
+
+static void mba6ul_setup_iomuxc_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(mba6ul_uart_pads,
+					 ARRAY_SIZE(mba6ul_uart_pads));
+}
+
+/* SD card on USDHC1 */
+static const iomux_v3_cfg_t mba6ul_usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK |	MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD |	MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 |	MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 |	MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 |	MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 |	MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* WP */
+	MX6_PAD_UART1_CTS_B__GPIO1_IO18 |	MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 |	MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC1_WP_GPIO	IMX_GPIO_NR(1, 18)
+
+static struct fsl_esdhc_cfg mba6ul_usdhc1_cfg = {
+	.esdhc_base = USDHC1_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int tq_bb_board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC1_BASE_ADDR)
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+
+	return ret;
+}
+
+int tq_bb_board_mmc_getwp(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	if (cfg->esdhc_base == USDHC1_BASE_ADDR)
+		ret = gpio_get_value(USDHC1_WP_GPIO);
+
+	return ret;
+}
+
+int tq_bb_board_mmc_init(struct bd_info *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(mba6ul_usdhc1_pads,
+					 ARRAY_SIZE(mba6ul_usdhc1_pads));
+	gpio_request(USDHC1_CD_GPIO, "usdhc1-cd");
+	gpio_request(USDHC1_WP_GPIO, "usdhc1-wp");
+	gpio_direction_input(USDHC1_CD_GPIO);
+	gpio_direction_input(USDHC1_WP_GPIO);
+
+	mba6ul_usdhc1_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	if (fsl_esdhc_initialize(bis, &mba6ul_usdhc1_cfg))
+		puts("Warning: failed to initialize SD card\n");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	tq_bb_board_early_init_f();
+
+	mba6ul_setup_iomuxc_uart();
+
+	return 0;
+}
+
+/*
+ * This is done per baseboard to allow different implementations
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 bmode = imx6_src_get_boot_mode();
+	u8 imx6_bmode = (bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
+
+	/* USB boot */
+	if (spl_boot_device() == BOOT_DEVICE_BOARD) {
+		printf("USB\n");
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		return;
+	}
+
+	switch (imx6_bmode) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		/* SD/eSD - BOOT_DEVICE_MMC2 */
+		printf("SD\n");
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		break;
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/* MMC/eMMC - BOOT_DEVICE_MMC1 */
+		printf("eMMC\n");
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		break;
+	case IMX6_BMODE_QSPI:
+		/* QSPI - BOOT_DEVICE_SPI */
+		printf("QSPI\n");
+		spl_boot_list[0] = BOOT_DEVICE_NOR;
+		break;
+	case IMX6_BMODE_SERIAL_ROM:
+		/* SERIAL_ROM - BOOT_DEVICE_BOARD */
+		printf("Serial ROM\n");
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		break;
+	default:
+		printf("WARNING: unknown boot device, fallback to eMMC\n");
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		break;
+	}
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	/* Longest FDT name */
+	char dt[] = "imx6ull-tqma6ull2l-mba6ulx";
+	enum tqma6ul_som_type somtype;
+
+	somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx");
+	if (somtype == tqma6ul_som_type_unknown)
+		return -EINVAL;
+
+	if (!strcmp(name, dt))
+		return -EINVAL;
+
+	printf("Device tree: %s\n", name);
+	return 0;
+}
diff --git a/board/tq/tqma6ul/spl_tqma6ul_ram.c b/board/tq/tqma6ul/spl_tqma6ul_ram.c
new file mode 100644
index 00000000000..c5d50890702
--- /dev/null
+++ b/board/tq/tqma6ul/spl_tqma6ul_ram.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ */
+
+#include <config.h>
+#include <hang.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6ul-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
+
+#include "../common/tq_som.h"
+
+static void tqma6ul_init_ddr_controller(u32 size)
+{
+	/* TQMa6ul DDR config */
+
+	/* reset DDR via Chip Select 0*/
+	tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x03180000);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000);
+
+	debug("SPL: tqma6ul ddr iomux ....\n");
+
+	/* DDR IO TYPE: */
+	tq_som_init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000);
+	tq_som_init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000);
+	/* CLOCK: */
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDCLK_0, 0x00000030);
+	/* Control: */
+	tq_som_init_write_reg(MX6_IOM_DRAM_CAS, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_RAS, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000);
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDODT0, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDODT1, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_GRP_CTLDS, 0x00000030);
+	/* Data Strobes: */
+	tq_som_init_write_reg(MX6_IOM_DDRMODE_CTL, 0x00020000);
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDQS0, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_SDQS1, 0x00000030);
+	/* Data: */
+	tq_som_init_write_reg(MX6_IOM_GRP_DDRMODE, 0x00020000);
+	tq_som_init_write_reg(MX6_IOM_GRP_B0DS, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_GRP_B1DS, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030);
+	tq_som_init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030);
+
+	debug("tqma6ul ddr controller registers ....\n");
+
+	/* MMDC_MDSCR - MMDC Core Special Command Register */
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);
+
+	debug("tqma6ul ddr calibrations ....\n");
+
+	/* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */
+	tq_som_init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003);
+
+	switch (size) {
+	case SZ_512M:
+		if (IS_ENABLED(CONFIG_MX6UL)) {
+			debug("tqma6ul ddr calibration standard variant ....\n");
+
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41580150);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E52);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4A);
+
+		} else if (IS_ENABLED(CONFIG_MX6ULL)) {
+			if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) {
+				debug("tqma6ull ddr calibration standard variant ....\n");
+
+				tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00090009);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x4140013C);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E26);
+
+			} else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) {
+				debug("tqma6ull ddr calibration lga variant ....\n");
+
+				tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00050009);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41340130);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E);
+				tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E28);
+
+			} else {
+				pr_err("invalid/unsupported SoM variant ....\n");
+				hang();
+			} /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */
+		} else {
+			pr_err("ERROR: invalid/unsupported CPU variant ....\n");
+			hang();
+		} /* IS_ENABLED(CONFIG_MX6UL) */
+		break;
+	case SZ_256M:
+		if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) {
+			debug("tqma6ul ddr calibration standard variant ....\n");
+
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41480144);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E54);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E48);
+
+		} else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) {
+			debug("tqma6ul ddr calibration lga variant ....\n");
+
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00130003);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41540154);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40405050);
+			tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4C);
+
+		} else {
+			pr_err("ERROR: invalid/unsupported SoM variant ....\n");
+			hang();
+		} /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */
+		break;
+	default:
+		pr_err("ERROR: invalid/unsupported RAM size ....\n");
+		hang();
+		break;
+	}
+
+	tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333);
+	tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333);
+
+	tq_som_init_write_reg(0x021B082C, 0xf3333333); /* MMDC_MPWRDQBY0DL */
+	tq_som_init_write_reg(0x021B0830, 0xf3333333); /* MMDC_MPWRDQBY1DL */
+	tq_som_init_write_reg(0x021B08C0, 0x00921012); /* MMDC_MPDCCR */
+
+	/*
+	 * Complete calibration by forced measurement:
+	 */
+	tq_som_init_write_reg(MX6_MMDC_P0_MPMUR0, 0x00000800);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002002D);
+
+	debug("tqma6ul ddr mmdc ....\n");
+
+	tq_som_init_write_reg(MX6_MMDC_P0_MDOTC, 0x00333030);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDCFG0, 0x676B52F3);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB66D8B63);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDMISC, 0x00201740);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDOR, 0x006B1023);
+
+	switch (size) {
+	case SZ_512M:
+		tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x0000004F);
+		tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x84180000);
+		break;
+	case SZ_256M:
+		tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x00000047);
+		tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000);
+		break;
+	default:
+		hang();
+		break;
+	}
+
+	debug("tqma6ul ddr cs0 ....\n");
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x02008032);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDREF, 0x00000800);
+	tq_som_init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00000227);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D);
+	tq_som_init_write_reg(MX6_MMDC_P0_MAPSR, 0x00011006);
+	tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00000000);
+}
+
+void tq_som_ram_init(void)
+{
+	int i;
+	/* RAM sizes need to be in descending order */
+	static const u32 ram_sizes[] = {
+#if IS_ENABLED(CONFIG_TQMA6UL_RAM_512M)
+		SZ_512M,
+#endif
+#if IS_ENABLED(CONFIG_TQMA6UL_RAM_256M)
+		SZ_256M,
+#endif
+	};
+
+	if (!is_mx6ul() && !is_mx6ull()) {
+		pr_err("ERROR: Not running on TQMa6UL[L]\n");
+		hang();
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) {
+		tqma6ul_init_ddr_controller(ram_sizes[i]);
+		if (tq_som_ram_check_size(ram_sizes[i]))
+			break;
+	}
+
+	if (i < ARRAY_SIZE(ram_sizes)) {
+		debug("SPL: tqma6ul ddr init done ...\n");
+	} else {
+		pr_err("ERROR: Invalid DDR RAM size\n");
+		hang();
+	}
+}
diff --git a/board/tq/tqma6ul/tqma6ul.c b/board/tq/tqma6ul/tqma6ul.c
new file mode 100644
index 00000000000..999396f573d
--- /dev/null
+++ b/board/tq/tqma6ul/tqma6ul.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Marco Felsch, Nora Schiffer
+ *
+ */
+
+#include <env.h>
+#include <fdt_support.h>
+#include <mmc.h>
+#include <mtd_node.h>
+#include <spi_flash.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#include "../common/tq_bb.h"
+#include "tqma6ul.h"
+
+int tq_bb_board_early_init_f(void)
+{
+	if (CONFIG_IS_ENABLED(FSL_QSPI))
+		enable_qspi_clk(0);
+
+	return 0;
+}
+
+/**
+ * Checks if CPU (imx6ul or ima6ull) matches the one set for the image.
+ */
+static const char *check_cpu_variant(void)
+{
+	const char *cpu;
+
+	if (is_mx6ul()) {
+		cpu = "ul";
+		if (!IS_ENABLED(CONFIG_MX6UL))
+			printf("*** ERROR: image not compiled for i.MX6UL!\n");
+	} else if (is_mx6ull()) {
+		cpu = "ull";
+		if (!IS_ENABLED(CONFIG_MX6ULL))
+			printf("*** ERROR: image not compiled for i.MX6ULL!\n");
+	} else {
+		printf("unknown CPU\n");
+		return NULL;
+	}
+
+	return cpu;
+}
+
+/**
+ * Checks configuration for TQMa6UL SoM module variant.
+ */
+enum tqma6ul_som_type check_tqma6ul_variant(void)
+{
+	if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))
+		return tqma6ul_som_type_ca;
+
+	if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))
+		return tqma6ul_som_type_lga;
+
+	printf("unknown SoM variant\n");
+
+	return tqma6ul_som_type_unknown;
+}
+
+/**
+ * Adjusts device tree name based on CPU variant.
+ */
+enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb)
+{
+	const char *tqma6ul_cpu, *tqma6ul_variant;
+	enum tqma6ul_som_type somtype;
+	u8 mx6ul_variant;
+
+	tqma6ul_cpu = check_cpu_variant();
+	if (!tqma6ul_cpu)
+		return tqma6ul_som_type_unknown;
+
+	/* MX6UL1 vs MX6UL2 */
+	mx6ul_variant = check_module_fused(MODULE_ENET2) ? 1 : 2;
+
+	somtype = check_tqma6ul_variant();
+	switch (somtype) {
+	case tqma6ul_som_type_ca:
+		tqma6ul_variant = "";
+		break;
+	case tqma6ul_som_type_lga:
+		tqma6ul_variant = "l";
+		break;
+	default:
+		return tqma6ul_som_type_unknown;
+	}
+
+	snprintf(dt, dtsize, "imx6%s-tqma6%s%u%s-%s",
+		 tqma6ul_cpu, tqma6ul_cpu, mx6ul_variant, tqma6ul_variant, mb);
+
+	return somtype;
+}
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD)
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+const char *tq_som_get_modulename(void)
+{
+	if (is_mx6ul()) {
+		if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))
+			return "TQMa6ULx";
+
+		if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))
+			return "TQMa6ULxL";
+	}
+
+	if (is_mx6ull()) {
+		if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD))
+			return "TQMa6ULLx";
+
+		if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA))
+			return "TQMa6ULLxL";
+	}
+
+	return "Unknown";
+}
+
+int checkboard(void)
+{
+	printf("Board: %s on %s\n", tq_som_get_modulename(),
+	       tq_bb_get_boardname());
+
+	return tq_bb_checkboard();
+}
+
+#if IS_ENABLED(CONFIG_CMD_BMODE)
+static const struct boot_mode tqma6ul_board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
+
+int tq_bb_board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_CMD_BMODE))
+		add_board_boot_modes(tqma6ul_board_boot_modes);
+
+	env_set_runtime("board_name", tq_som_get_modulename());
+
+	return 0;
+}
+
+int tq_bb_checkboard(void)
+{
+	if (is_mx6ul()) {
+		if (!IS_ENABLED(CONFIG_MX6UL))
+			printf("*** ERROR: image not compiled for i.MX6UL!\n");
+	} else if (is_mx6ull()) {
+		if (!IS_ENABLED(CONFIG_MX6ULL))
+			printf("*** ERROR: image not compiled for i.MX6ULL!\n");
+	} else {
+		printf("*** ERROR: unknown CPU variant!\n");
+	}
+
+	return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)
+int tq_bb_ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */
+
+#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */
diff --git a/board/tq/tqma6ul/tqma6ul.cfg b/board/tq/tqma6ul/tqma6ul.cfg
new file mode 100644
index 00000000000..42821ae5c7a
--- /dev/null
+++ b/board/tq/tqma6ul/tqma6ul.cfg
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+#if IS_ENABLED(CONFIG_QSPI_BOOT)
+BOOT_FROM	qspi
+#else
+BOOT_FROM	sd
+#endif
+
+#if IS_ENABLED(CONFIG_IMX_HAB)
+CSF CONFIG_CSF_SIZE
+#endif
diff --git a/board/tq/tqma6ul/tqma6ul.env b/board/tq/tqma6ul/tqma6ul.env
new file mode 100644
index 00000000000..fa172caca23
--- /dev/null
+++ b/board/tq/tqma6ul/tqma6ul.env
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ *
+ * TQMa6UL environment
+ */
+
+#include <env/tq/tq-imx-shared.env>
+
+board=tqma6ul
+boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}"
+emmc_bootp_start=TQMA6UL_MMC_UBOOT_SECTOR_START
+emmc_dev=0
+fdt_addr_r=TQMA6UL_FDT_ADDRESS
+fdtoverlay_addr_r=TQMA6UL_FDT_OVERLAY_ADDR
+image=zImage
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+mmcautodetect=yes
+mmcblkdev=0
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+netdev=eth1
+pxefile_addr_r=CONFIG_SYS_LOAD_ADDR
+ramdisk_addr_r=TQMA6UL_INITRD_ADDRESS
+sd_dev=1
+uboot=u-boot-with-spl.imx
+uboot_mmc_start=TQMA6UL_MMC_UBOOT_SECTOR_START
+uboot_mmc_size=TQMA6UL_MMC_UBOOT_SECTOR_COUNT
+uboot_spi_sector_size=TQMA6UL_SPI_FLASH_SECTOR_SIZE
+uboot_spi_start=TQMA6UL_SPI_UBOOT_START
+uboot_spi_size=TQMA6UL_SPI_UBOOT_SIZE
+
+#ifdef CONFIG_USB_FUNCTION_FASTBOOT
+
+/* 0=user 1=boot1 2=boot2 */
+fastboot_mmc_boot_partition = 1
+
+fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0
+
+fastboot_raw_partition_bootloader=
+	TQMA6UL_MMC_UBOOT_SECTOR_START TQMA6UL_MMC_UBOOT_SECTOR_COUNT mmcpart
+	"${fastboot_mmc_boot_partition}"
+
+fastbootcmd=fastboot usb 0
+
+#endif /* CONFIG_USB_FUNCTION_FASTBOOT */
diff --git a/board/tq/tqma6ul/tqma6ul.h b/board/tq/tqma6ul/tqma6ul.h
new file mode 100644
index 00000000000..595edc89e19
--- /dev/null
+++ b/board/tq/tqma6ul/tqma6ul.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Max Merchel
+ */
+
+enum tqma6ul_som_type {
+	/* unknown */
+	tqma6ul_som_type_unknown,
+	/* connector module */
+	tqma6ul_som_type_ca,
+	/* LGA Variant */
+	tqma6ul_som_type_lga,
+};
+
+/**
+ * Checks configuration for TQMa6UL SoM module variant
+ */
+enum tqma6ul_som_type check_tqma6ul_variant(void);
+
+/**
+ * Adjusts device tree name based on CPU variant.
+ */
+enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb);
diff --git a/board/tq/tqma6ul/tqma6ul_mba6ul.c b/board/tq/tqma6ul/tqma6ul_mba6ul.c
new file mode 100644
index 00000000000..be78060cbda
--- /dev/null
+++ b/board/tq/tqma6ul/tqma6ul_mba6ul.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Marco Felsch, Nora Schiffer
+ */
+
+#include <env.h>
+#include <malloc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/mach-imx/sys_proto.h>
+
+#include "../common/tq_bb.h"
+#include "tqma6ul.h"
+
+const char *tq_bb_get_boardname(void)
+{
+	return "MBa6ULx";
+}
+
+int board_early_init_f(void)
+{
+	return tq_bb_board_early_init_f();
+}
+
+static void mba6ul_setup_eth(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	if (check_module_fused(MODULE_ENET1)) {
+		printf("FEC1: disabled by fuses\n");
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17]
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+		enable_fec_anatop_clock(0, ENET_50MHZ);
+	}
+
+	if (check_module_fused(MODULE_ENET2)) {
+		printf("FEC2: disabled by fuses\n");
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET2,
+		 * clear gpr1[14], set gpr1[18]
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+		enable_fec_anatop_clock(1, ENET_50MHZ);
+	}
+
+	enable_enet_clk(1);
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+static void mba6ul_set_fdt_file(void)
+{
+	/* Longest FDT name */
+	char dt[] = "imx6ull-tqma6ull2l-mba6ulx.dtb";
+	enum tqma6ul_som_type somtype;
+
+	if (!env_get("fdtfile")) {
+		somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx.dtb");
+		if (somtype == tqma6ul_som_type_unknown)
+			return;
+
+		env_set_runtime("fdtfile", dt);
+	}
+}
+
+int board_late_init(void)
+{
+	unsigned int bmode =
+		(imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
+
+	tq_bb_board_late_init();
+
+	printf("Boot: ");
+
+	switch (bmode) {
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		printf("eMMC\n");
+		env_set_runtime("boot_dev", "mmc");
+		board_late_mmc_env_init();
+		break;
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		printf("SD\n");
+		env_set_runtime("boot_dev", "mmc");
+		board_late_mmc_env_init();
+		break;
+	case IMX6_BMODE_QSPI:
+	case IMX6_BMODE_NOR:
+		printf("QSPI\n");
+		env_set_runtime("boot_dev", "qspi");
+		break;
+	default:
+		printf("unhandled boot device %u\n", bmode);
+	}
+
+	mba6ul_set_fdt_file();
+	mba6ul_setup_eth();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	unsigned int port = (imx6_src_get_boot_mode() >> 11) & 0x3;
+
+	switch (port) {
+	case 0:
+		/* SDHC1 - SD card on MBa6ULx */
+		return 1;
+
+	default:
+		/* Return eMMC device otherwise */
+		return 0;
+	}
+}
+
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return tq_bb_ft_board_setup(blob, bd);
+}
+#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */
diff --git a/board/tq/tqma7/tqma7.c b/board/tq/tqma7/tqma7.c
index 30bd155713d..ccf805d5461 100644
--- a/board/tq/tqma7/tqma7.c
+++ b/board/tq/tqma7/tqma7.c
@@ -17,6 +17,7 @@
 
 #include "../common/tq_bb.h"
 #include "../common/tq_som.h"
+#include "../common/tq_sysinfo.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +55,7 @@ static const char *tqma7_get_boardname(void)
 int board_late_init(void)
 {
 	const char *bname = tqma7_get_boardname();
+	int ret;
 
 	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
 		struct tag_serialnr serialnr;
@@ -65,6 +67,10 @@ int board_late_init(void)
 
 	env_set_runtime("board_name", bname);
 
+	ret = tq_common_sysinfo_setup();
+	if (ret)
+		log_err("Sysinfo setup failed: %d\n", ret);
+
 	return tq_bb_board_late_init();
 }
 
diff --git a/board/tq/tqma7/tqma7.env b/board/tq/tqma7/tqma7.env
index 857f16d11bb..05035078869 100644
--- a/board/tq/tqma7/tqma7.env
+++ b/board/tq/tqma7/tqma7.env
@@ -28,8 +28,15 @@ uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE
 uboot_spi_start=TQMA7_SPI_UBOOT_START
 uboot_spi_size=TQMA7_SPI_UBOOT_SIZE
 
-#ifdef CONFIG_FASTBOOT_UUU_SUPPORT
+#ifdef CONFIG_USB_FUNCTION_FASTBOOT
+
+/* 0=user 1=boot1 2=boot2 */
+fastboot_mmc_boot_partition = 1
+
 fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0
-fastboot_raw_partition_bootloader=TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart 1
+fastboot_raw_partition_bootloader=
+	TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart
+	"${fastboot_mmc_boot_partition}"
 fastbootcmd=fastboot usb 0
+
 #endif
diff --git a/board/traverse/common/Kconfig b/board/traverse/common/Kconfig
index d34832bd0d3..96b2566b697 100644
--- a/board/traverse/common/Kconfig
+++ b/board/traverse/common/Kconfig
@@ -2,5 +2,5 @@ config TEN64_CONTROLLER
 	bool "Enable Ten64 board controller driver"
 	depends on TARGET_TEN64
 	help
-		Support for the board microcontroller on the Traverse
-		Ten64 family of boards.
+	  Support for the board microcontroller on the Traverse
+	  Ten64 family of boards.
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index ac8c9a9a81a..5c45f9932c5 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -148,7 +148,7 @@ int fsl_initdram(void)
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
-	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_size(gd->dram[0].size + gd->dram[1].size, "");
 	print_ddr_info(0);
 }
 
@@ -277,8 +277,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	/* fixup DT for the two GPP DDR banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		base[i] = gd->bd->bi_dram[i].start;
-		size[i] = gd->bd->bi_dram[i].size;
+		base[i] = gd->dram[i].start;
+		size[i] = gd->dram[i].size;
 		/* reduce size if reserved memory is within this bank */
 		if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i))
 			size[i] = gd->arch.resv_ram - base[i];
diff --git a/board/variscite/omap4_var_som/Kconfig b/board/variscite/omap4_var_som/Kconfig
new file mode 100644
index 00000000000..dc943b3366e
--- /dev/null
+++ b/board/variscite/omap4_var_som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP4_VAR_SOM
+
+config SYS_BOARD
+	default "omap4_var_som"
+
+config SYS_VENDOR
+	default "variscite"
+
+config SYS_CONFIG_NAME
+	default "ti_omap4_common"
+
+endif
diff --git a/board/variscite/omap4_var_som/MAINTAINERS b/board/variscite/omap4_var_som/MAINTAINERS
new file mode 100644
index 00000000000..a8680bc75d3
--- /dev/null
+++ b/board/variscite/omap4_var_som/MAINTAINERS
@@ -0,0 +1,4 @@
+ARM OMAP4 VARISCITE VAR-SOM-OM44 MODULE
+M:	Bastien Curutchet <bastien.curutchet@bootlin.com>
+S:	Maintained
+N:	omap4_var_som
diff --git a/board/variscite/omap4_var_som/Makefile b/board/variscite/omap4_var_som/Makefile
new file mode 100644
index 00000000000..c88ab3cac7b
--- /dev/null
+++ b/board/variscite/omap4_var_som/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= omap4_var_som.o
diff --git a/board/variscite/omap4_var_som/omap4_var_som.c b/board/variscite/omap4_var_som/omap4_var_som.c
new file mode 100644
index 00000000000..f2fc790dd4b
--- /dev/null
+++ b/board/variscite/omap4_var_som/omap4_var_som.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm-generic/gpio.h>
+#include <env.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <serial.h>
+
+#include "omap4_var_som_mux.h"
+
+#define VAR_SOM_REV_GPIO		   52
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 VAR-SOM-OM44\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * Return: 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_VAR_SOM;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+static const struct emif_regs emif_regs_hynix_kdpm_400_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb2,
+	.sdram_config			= 0x80001ab2,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_hynix_kdpm_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 rev;
+
+	gpio_direction_input(VAR_SOM_REV_GPIO);
+	rev = gpio_get_value(VAR_SOM_REV_GPIO);
+
+	if (rev == 1)
+		*regs = &emif_regs_hynix_kdpm_400_mhz_1cs;
+	else
+		*regs = &emif_regs_hynix_kdpm_400_mhz_2cs;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else if (omap_rev == OMAP4430_ES2_3)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else if (omap_rev < OMAP4460_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else
+		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+			     const struct lpddr2_device_timings **cs0_device_timings,
+			     const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+	*cs1_device_timings = NULL;
+}
+
+/**
+ * @brief misc_init_r() - VAR-SOM configuration
+ *
+ * Configure VAR-SOM board specific configurations such as power configurations.
+ *
+ * Return: 0
+ */
+int misc_init_r(void)
+{
+	u32 auxclk, altclksrc;
+
+	auxclk = readl(&scrm->auxclk3);
+	/* Select sys_clk */
+	auxclk &= ~AUXCLK_SRCSELECT_MASK;
+	auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+	/* Set the divisor to 2 */
+	auxclk &= ~AUXCLK_CLKDIV_MASK;
+	auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+	/* Request auxilary clock #3 */
+	auxclk |= AUXCLK_ENABLE_MASK;
+
+	writel(auxclk, &scrm->auxclk3);
+
+	altclksrc = readl(&scrm->altclksrc);
+
+	/* Activate alternate system clock supplier */
+	altclksrc &= ~ALTCLKSRC_MODE_MASK;
+	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+	/* enable clocks */
+	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+	writel(altclksrc, &scrm->altclksrc);
+
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		do_set_mux((*ctrl)->control_padconf_core_base,
+			   core_padconf_array_essential,
+			   sizeof(core_padconf_array_essential) /
+			   sizeof(struct pad_conf_entry));
+
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
+			   wkup_padconf_array_essential,
+			   sizeof(wkup_padconf_array_essential) /
+			   sizeof(struct pad_conf_entry));
+	}
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	if (IS_ENABLED(CONFIG_MMC))
+		return omap_mmc_init(0, 0, 0, -1, -1);
+}
diff --git a/board/variscite/omap4_var_som/omap4_var_som_mux.h b/board/variscite/omap4_var_som/omap4_var_som_mux.h
new file mode 100644
index 00000000000..fe0b99daf75
--- /dev/null
+++ b/board/variscite/omap4_var_som/omap4_var_som_mux.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _VAR_SOM_OM44_MUX_DATA_H_
+#define _VAR_SOM_OM44_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat3 */
+{GPMC_NCS2, (PTD | IEN | M3)},  /* gpio52 som rev */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},  /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_cmd */
+{I2C1_SCL, (PTU | IEN | M0)},  /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},  /* i2c1_sda */
+{UART3_RX_IRRX, (IEN | M0)},  /* uart3_rx */
+{UART3_TX_IRTX, (M0)},  /* uart3_tx */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+{PAD0_FREF_SLICER_IN, (M0)},  /* fref_slicer_in */
+{PAD1_FREF_CLK_IOREQ, (M0)},  /* fref_clk_ioreq */
+{PAD0_FREF_CLK0_OUT, (M2)},  /* sys_drm_msecure */
+{PAD1_SYS_32K, (IEN | M0)},  /* sys_32k */
+{PAD0_SYS_NRESPWRON, (M0)},  /* sys_nrespwron */
+{PAD1_SYS_NRESWARM, (M0)},  /* sys_nreswarm */
+{PAD0_SYS_PWR_REQ, (PTU | M0)},  /* sys_pwr_req */
+};
+
+#endif /* _VAR_SOM_OM44_MUX_DATA_H_ */
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 5c3240da073..07fc8da1b71 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -67,7 +67,7 @@ config BOOT_SCRIPT_OFFSET
 	default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
 	default 0 if TARGET_XILINX_MBV
 	help
-	   Specifies distro boot script offset in NAND/QSPI/NOR flash.
+	  Specifies distro boot script offset in NAND/QSPI/NOR flash.
 
 config CMD_FRU
 	bool "FRU information for product"
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 89562ef77fc..52a2e8767d8 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -14,8 +14,12 @@
 #include <init.h>
 #include <jffs2/load_kernel.h>
 #include <log.h>
+#include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/sections.h>
+#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2)
+#include <asm/arch/hardware.h>
+#endif
 #include <dm/uclass.h>
 #include <i2c.h>
 #include <linux/sizes.h>
@@ -30,6 +34,8 @@
 #include <rng.h>
 #include <slre.h>
 #include <soc.h>
+#include <zynqmp_firmware.h>
+#include <linux/bitfield.h>
 #include <linux/ctype.h>
 #include <linux/kernel.h>
 #include <u-boot/uuid.h>
@@ -718,7 +724,74 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 
 	return reg + size;
 }
+#endif
+
+#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
+
+#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2)
+/*
+ * The Versal and Versal Gen 2 PMC Global pggs4 register contains below
+ * information in each byte as:
+ *
+ * Byte[3]: Magic number
+ * Byte[2]: Boot counter value
+ * Byte[1]: Boot partition value - boot index
+ * Byte[0]: Rollback counter value
+ */
+
+#define MAGIC_NUM	0x1D
+#define MAGIC_MASK	GENMASK(31, 24)
+#define BOOTINDEX_MASK	GENMASK(15, 8)
+
+static int plat_get_boot_index(void)
+{
+	u32 val;
+
+	if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
+		val = zynqmp_pm_get_pmc_global_pggs_reg(PMC_GLOBAL_PGGS4_REG);
+	else
+		val = readl(PMC_GLOBAL_PGGS4_REG);
+
+	if (FIELD_GET(MAGIC_MASK, val) != MAGIC_NUM) {
+		log_err("FWU requires PMC magic number 0x%x\n", MAGIC_NUM);
+		return -EINVAL;
+	}
+
+	return FIELD_GET(BOOTINDEX_MASK, val);
+}
+#endif
+
+int fwu_plat_get_alt_num(struct udevice __always_unused *dev,
+			 efi_guid_t *image_id, u8 *alt_num)
+{
+	int ret;
+
+	ret = fwu_mtd_get_alt_num(image_id, alt_num, "nor0");
+	debug("%s: return %d\n", __func__, ret);
+
+	return ret;
+}
 
+void fwu_plat_get_bootidx(uint *boot_idx)
+{
+	int ret;
+	u32 active_idx;
+
+	ret = fwu_get_active_index(&active_idx);
+	if (ret < 0)
+		printf("%s: failed to read active index\n", __func__);
+
+	ret = plat_get_boot_index();
+	if (ret < 0) {
+		*boot_idx = 0;
+		printf("%s: failed and setup boot index to 0\n", __func__);
+	} else {
+		*boot_idx = ret;
+	}
+
+	debug("%s: boot_idx: %d, active_idx: %d\n",
+	      __func__, *boot_idx, active_idx);
+}
 #endif
 
 #if IS_ENABLED(CONFIG_BOARD_RNG_SEED)
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 9371c30ea27..8666f2ceff4 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -10,6 +10,7 @@
 #include <env.h>
 #include <efi_loader.h>
 #include <fdtdec.h>
+#include <fwu.h>
 #include <init.h>
 #include <env_internal.h>
 #include <log.h>
@@ -293,7 +294,8 @@ int board_late_init(void)
 {
 	int ret;
 
-	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) &&
+	    !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE))
 		configure_capsule_updates();
 
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
@@ -374,6 +376,8 @@ enum env_location env_get_location(enum env_operation op, int prio)
 
 #define DFU_ALT_BUF_LEN		SZ_1K
 
+#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \
+	!defined(CONFIG_FWU_MULTI_BANK_UPDATE)
 static void mtd_found_part(u32 *base, u32 *size)
 {
 	struct mtd_info *part, *mtd;
@@ -450,3 +454,39 @@ void configure_capsule_updates(void)
 	update_info.dfu_string = strdup(buf);
 	debug("Capsule DFU: %s\n", update_info.dfu_string);
 }
+#endif
+
+#if defined(CONFIG_FWU_MULTI_BANK_UPDATE)
+
+/* Generate dfu_alt_info from partitions */
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	int ret;
+	struct mtd_info *mtd;
+
+	/*
+	 * It is called multiple times for every image
+	 * per bank that's why enough to set it up once.
+	 */
+	if (env_get("dfu_alt_info"))
+		return;
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+	memset(buf, 0, DFU_ALT_BUF_LEN);
+
+	mtd_probe_devices();
+
+	mtd = get_mtd_device_nm("nor0");
+	if (IS_ERR_OR_NULL(mtd))
+		return;
+
+	ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd);
+	if (ret < 0) {
+		log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret);
+		return;
+	}
+	log_debug("Make dfu_alt_info: '%s'\n", buf);
+
+	env_set("dfu_alt_info", buf);
+}
+#endif
diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c
index 05ecb75406b..d8eff203a56 100644
--- a/board/xilinx/zynq/cmds.c
+++ b/board/xilinx/zynq/cmds.c
@@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr)
 		 * This validation is just for PS DDR.
 		 * TODO: Update this for PL DDR check as well.
 		 */
-		if (part_load_addr < gd->bd->bi_dram[0].start &&
+		if (part_load_addr < gd->dram[0].start &&
 		    ((part_load_addr + part_data_len) >
-		    (gd->bd->bi_dram[0].start +
-		     gd->bd->bi_dram[0].size))) {
+		    (gd->dram[0].start +
+		     gd->dram[0].size))) {
 			printf("INVALID_LOAD_ADDRESS_FAIL\n");
 			return -1;
 		}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index a1d8ae26673..a12c039d8c9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -279,8 +279,8 @@ int dram_init(void)
 #else
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = get_effective_memsize();
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = get_effective_memsize();
 
 	mem_map_fill();
 
@@ -541,10 +541,6 @@ int board_late_init(void)
 {
 	int ret, multiboot;
 
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
-	usb_ether_init();
-#endif
-
 	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
 		configure_capsule_updates();
 
diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c
index 38340b33c8b..894c2ef293c 100644
--- a/board/zyxel/nsa325/nsa325.c
+++ b/board/zyxel/nsa325/nsa325.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2014-2025 Tony Dinh <mibodhi@gmail.com>
  *
  * Based on
  * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
@@ -51,11 +51,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define HDD1_GREEN_LED		BIT(9)
 #define HDD1_RED_LED		BIT(10)
 #define HDD2_POWER		BIT(15)
-#define WATCHDOG_SIGNAL		BIT(14)
 
 #define NSA325_OE_HIGH		(~(COPY_GREEN_LED | COPY_RED_LED | \
-				   HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL))
-#define NSA325_VAL_HIGH		(WATCHDOG_SIGNAL | HDD2_POWER)
+				   HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER))
+#define NSA325_VAL_HIGH		(HDD2_POWER)
 
 #define BTN_POWER				46
 #define BTN_RESET				36