Merge tag 'xilinx-for-v2026.10-rc1-v3' of https://git.u-boot-project.org/u-boot/custodians/u-boot-amdHEADmaster

AMD/Xilinx/FPGA changes for v2026.10-rc1 v3

AMD:
- Firmware interface decoupling (part 1)

ZynqMP:
- DT updates
- Add TCG variant detection

Versal/Versal2:
- Drop DDR MMU mapping and map it dynamically

tools:
- Add register initialization to mkimage

MAINTAINERS:
- Clean Zynq/ZynqMP fragments

ufs:
- Fix driver reregistration

fpga:
- altera: Simplify driver conditional compilation selection

4 files changed, 95 insertions, 5 deletions

diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index ea14ed4ef95..6052a31b5b4 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -7,6 +7,7 @@
  */
 
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <cpu_func.h>
 #include <dm.h>
@@ -16,6 +17,7 @@
 #include <zynqmp_firmware.h>
 #include <asm/cache.h>
 #include <asm/ptrace.h>
+#include <asm/system.h>
 #include <linux/bitfield.h>
 
 #if defined(CONFIG_ZYNQMP_IPI)
@@ -326,6 +328,93 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
 }
 #endif
 
+#if defined(CONFIG_ARCH_VERSAL)
+u32 versal_pmc_multi_boot(void)
+{
+	/* At EL3 the SMC path to firmware is unavailable, read directly */
+	if (current_el() == 3)
+		return versal_multi_boot_reg();
+
+	return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK;
+}
+
+u8 versal_get_bootmode(void)
+{
+	u32 reg;
+
+	/* At EL3 the SMC path to firmware is unavailable, read directly */
+	if (current_el() == 3)
+		reg = versal_bootmode_reg();
+	else
+		reg = zynqmp_pm_get_bootmode_reg();
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	return reg & BOOT_MODES_MASK;
+}
+#endif
+
+#if defined(CONFIG_ARCH_VERSAL_NET)
+u8 versal_net_get_bootmode(void)
+{
+	u32 reg;
+
+	/* At EL3 the SMC path to firmware is unavailable, read directly */
+	if (current_el() == 3)
+		reg = versal_net_bootmode_reg();
+	else
+		reg = zynqmp_pm_get_bootmode_reg();
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	return reg & BOOT_MODES_MASK;
+}
+#endif
+
+#if defined(CONFIG_ARCH_ZYNQMP)
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
+{
+	/* At EL3 or in SPL the firmware (SMC) path is unavailable */
+	if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
+		return zynqmp_mmio_rawwrite(address, mask, value);
+
+	return xilinx_pm_request(PM_MMIO_WRITE, address, mask, value,
+				 0, 0, 0, NULL);
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	/* At EL3 or in SPL the firmware (SMC) path is unavailable */
+	if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
+		return zynqmp_mmio_rawread(address, value);
+
+	ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, 0, 0, 0,
+				ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_ARCH_VERSAL2)
+u32 versal2_pmc_multi_boot(void)
+{
+	/* At EL3 the SMC path to firmware is unavailable, read directly */
+	if (current_el() == 3)
+		return versal2_multi_boot_reg();
+
+	return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK;
+}
+#endif
+
 int zynqmp_pm_feature(const u32 api_id)
 {
 	int ret;
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 822183c5785..69d7111a5f1 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,8 +12,7 @@
 /*
  *  Altera FPGA support
  */
-#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX)
 #include <asm/arch/misc.h>
 #endif
 #include <errno.h>
@@ -48,8 +47,7 @@ static const struct altera_fpga {
 #endif
 };
 
-#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX)
 int fpga_is_partial_data(int devnum, size_t img_len)
 {
 	/*
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 4abc73013eb..0e13e230914 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
 	} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
 		strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
 	} else if (device->variants & ZYNQMP_VARIANT_TEG) {
-		strlcat(priv->machine, "teg", sizeof(priv->machine));
+		/* Devices with TEG variant might be TEG or TCG family */
+		strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
+			"tcg" : "teg", sizeof(priv->machine));
 	}
 
 	return 0;
diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c
index 6c949b2ca76..3369d32d924 100644
--- a/drivers/ufs/ufs-amd-versal2.c
+++ b/drivers/ufs/ufs-amd-versal2.c
@@ -563,4 +563,5 @@ U_BOOT_DRIVER(ufs_versal2_pltfm) = {
 	.id		= UCLASS_UFS,
 	.of_match	= ufs_versal2_ids,
 	.probe		= ufs_versal2_probe,
+	.priv_auto	= sizeof(struct ufs_versal2_priv),
 };