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authorTom Rini <trini@konsulko.com>2026-07-06 18:26:12 -0600
committerTom Rini <trini@konsulko.com>2026-07-06 18:26:12 -0600
commitee5d46b45ec0c63f8f9dd1e816e0dac3452ccc3d (patch)
tree800cd9e204ca027144070101884c0d5d3c00130f /include/reset-uclass.h
parentece349ade2973e220f524ce59e59711cc919263f (diff)
parenta18265f1ccb7a272721ed4286ed3b5a6182ff424 (diff)
downloadu-boot-master.tar.gz
u-boot-master.zip
Merge branch 'next'HEADmasterWIP/06Jul2026
Diffstat (limited to 'include/reset-uclass.h')
-rw-r--r--include/reset-uclass.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/reset-uclass.h b/include/reset-uclass.h
index 9a0696dd1e3..7af090b60b5 100644
--- a/include/reset-uclass.h
+++ b/include/reset-uclass.h
@@ -77,6 +77,25 @@ struct reset_ops {
*/
int (*rst_deassert)(struct reset_ctl *reset_ctl);
/**
+ * rst_reset - Reset a HW module.
+ *
+ * This optional function triggers a reset pulse on the reset line.
+ * If not implemented, reset_reset() falls back to rst_assert(),
+ * udelay(@delay_us), then rst_deassert(); that delay is therefore
+ * observed only on the fallback path.
+ *
+ * When rst_reset is provided, @delay_us is controller-specific: the
+ * implementation should honour it if the hardware needs a minimum
+ * assertion time before release. It may ignore @delay_us when the
+ * pulse shape is fixed elsewhere (for example a firmware pulse).
+ *
+ * @reset_ctl: The reset signal to pulse.
+ * @delay_us: Minimum delay in microseconds between assert and
+ * deassert where applicable; see above.
+ * @return 0 if OK, or a negative error code.
+ */
+ int (*rst_reset)(struct reset_ctl *reset_ctl, ulong delay_us);
+ /**
* rst_status - Check reset signal status.
*
* @reset_ctl: The reset signal to check.