| Age | Commit message (Collapse) | Author |
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Cherry-pick and adapt the reverted commit 208f50b51622
("mtd: spinand: micron: correct MT29F2G01ABAGD parameters").
The original patch used older macro names. During the adaptation,
update these to the macros provided by Miquel Raynal in the mainline
kernel:
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP ->
SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP()
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP ->
SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP()
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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Amlogic has its own rsv-info API to interact with BBT, unifykeys, env
and other vendor-specific custom NAND storages.
Amlogic reserved region is usually located right after BL2 partition:
+-----------+-----------------+-------------+--------+
| | | | |
| BL2 | RESERVED | TPL | ... |
| | | | |
+-----------+-----------------+-------------+--------+
1024 pages 48 erase blocks 8MB
Below there is a map of RSV regions:
+-----+-----+-----------+-----------+-----+-----------+
| | | | | | |
| GAP | BBT | ENV | KEY | DTB | ... |
| | | | | | |
+-----+-----+-----------+-----------+-----+-----------+
eraseblocks: 4 4 8 8 4 20
The current patch introduces a correct operations with BBT region using
rsv-info API and formats.
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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The spinand_read_page()/spinand_write_page() functions can return a
positive value (bitflips corrected on success).
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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Make compiler happy:
```
drivers/mtd/nand/spi/esmt.c: In function 'f50l1g41lb_otp_rw':
drivers/mtd/nand/spi/esmt.c:185:16: error: unused variable 'pagesize'
185 | size_t pagesize = nanddev_page_size(nand);
| ^~~~~~~~
drivers/mtd/nand/spi/esmt.c:180:29: error: unused variable 'nand'
180 | struct nand_device *nand = spinand_to_nand(spinand);
```
Fixes: f2c5a912aefb ("mtd: spinand: esmt: introduce read/write OTP ops")
Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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U-Boot for ESMT driver reads from OTP with ECC enabled.
Enable ECC for OTP reads/writes to ensure consistent behaviour across
devices and improve data reliability.
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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In the generic code, ECC is disabled for OTP read/write operations.
To enable ECC in OTP for the ESMT driver, custom OTP read/write
callbacks must be implemented. This patch provides these callbacks.
This is adaptation of the spinand_otp_rw() function.
Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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Detected by CONFIG_FORTIFY_SOURCE option.
Fix patch fix following buffer overflow in Amlgoic BBT module:
[ 0.716769] ------------[ cut here ]------------
[ 0.721142] strlen: detected buffer overflow: 5 byte read of buffer size 4
[ 0.728039] WARNING: CPU: 0 PID: 1 at lib/string_helpers.c:1032 __fortify_report+0x54/0x64
[ 0.736107] Modules linked in:
[ 0.739127] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.12.10-sdkernel #1
[ 0.746454] Hardware name: SberDevices SberBoom (DT)
[ 0.751371] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 0.758268] pc : __fortify_report+0x54/0x64
[ 0.762408] lr : __fortify_report+0x54/0x64
[ 0.766547] sp : ffff80008002b910
[ 0.769825] x29: ffff80008002b910 x28: 0000000000000000 x27: ffff00000007d090
[ 0.776901] x26: 0000000000000000 x25: 0000000000000014 x24: ffff00000007d5c8
[ 0.783970] x23: ffff80008002b9f4 x22: 0000000000000018 x21: ffff800080f87c68
[ 0.791044] x20: 0000000000000000 x19: 0000000000000005 x18: 0000000000000006
[ 0.798116] x17: ffff00000fe1b0d8 x16: 000000000001f200 x15: ffff80008002b390
[ 0.805193] x14: 0000000000000000 x13: 3420657a69732072 x12: ffff80008002b6b8
[ 0.805714] Freeing initrd memory: 6804K
[ 0.812250] x11: 00000000ffffffea x10: ffff800080f2f910 x9 : 0000000000000001
[ 0.812261] x8 : c0000000fffffbff x7 : 0000000000005fe8 x6 : ffff800080f2f8b8
[ 0.812272] x5 : 0000000000015fa8 x4 : 0000000000000000 x3 : 0000000000000000
[ 0.837353] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000000176740
[ 0.844426] Call trace:
[ 0.846841] __fortify_report+0x54/0x64
[ 0.850636] __fortify_panic+0x10/0x14
[ 0.854344] nand_create_bbt+0x39c/0x3ec
[ 0.858225] nand_scan_with_ids+0x14f0/0x1740
[ 0.862538] meson_nfc_probe+0x514/0x7a8
[ 0.866419] pl��ɵ}�ɽ���0x68/0xc4
[ 0.870042] really_probe+0xbc/0x2a4
[ 0.873578] __driver_probe_device+0x78/0x12c
[ 0.877890] driver_probe_device+0x3c/0x10c
[ 0.882031] __driver_attach+0x94/0x160
0.905404] meson_nfc_driver_init+0x1c/0x28
[ 0.909630] do_one_initcall+0x80/0x20c
[ 0.913425] kernel_init_freeable+0x1d8/0x2ac
[ 0.917738] kernel_init+0x20/0x1dc
[ 0.921188] ret_from_fork+0x10/0x20
[ 0.924726] ---[ end trace 0000000000000000 ]---
[ 0.929365] ------------[ cut here ]------------
[ 0.933869] kernel BUG at lib/string_helpers.c:1040!
[ 0.938786] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
[ 0.945512] Modules linked in:
[ 0.948534] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Tainted: G W 6.12.10-sdkernel #1
[ 0.957328] Tainted: [W]=WARN
[ 0.960260] Hardware name: SberDevices Sbe��>��0c
[ 1.119390] kernel_init_freeable+0x1d8/0x2ac
[ 1.123703] kernel_init+0x20/0x1dc
[ 1.127153] ret_from_fork+0x10/0x20
[ 1.130694] Code: d503233f a9bf7bfd 910003fd 97ffffe4 (d4210000)
[ 1.136728] ---[ end trace 0000000000000000 ]---
[ 1.144120] note: swapper/0[1] exited with irqs disabled
[ 1.146651] note: swapper/0[1] exited with preempt_count 1
[ 1.152077] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 1.159592] SMP: stopping secondary CPUs
[ 1.163472] Kernel Offset: 0x80000 from 0xffff800080000000
[ 1.168898] PHYS_OFFSET: 0x0
[ 1.171744] CPU features: 0x00,00000080,00200000,0200420b
[ 1.177092] Memory Limit: none
[ 1.183040] Rebooting in 5 seconds..
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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1) Use MTD_OPS_AUTO_OOB: this places all magic bytes from OOB free areas
to the beginning of the buffer, so we can use 'memcmp()' to find
magic.
2) Use temporary small buffer for magic instead of internal OOB buffer
of 'nand_chip'.
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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The first 4 bytes are reserved for bad block data.
Fixes: a508e8875e13 ("mtd: spinand: Add initial support for Micron MT29F2G01ABAGD")
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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Amlogic uses own magic for BBT, own predefined values to mark bad/good
block in BBT. This makes impossible to tune already implemented BBT
parser to load Amlogic's BBT. This new parser disables the default one,
also overloading its currently implemented API: 'nand_markbad_bbt()',
'nand_isbad_bbt()', 'nand_isreserved_bbt()' and 'nand_create_bbt()'.
Signed-off-by: Arseniy Krasnov <AVKrasnov@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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This is needed to make JFFS2 work correctly. Otherwise cleanmarkers will
be under ECC engine (we don't have free bytes in OOB when ECC has 512B
step size), so after JFFS2 writes cleanmarkers, page become unavailable
to write data on it later - such page considered already written and
need to be erased to save data correctly. This dirty trick makes JFFS2
to think that cleanmarkers are written successfully while in fact page
still untouched, so JFFS2 driver could write data on it later.
TODO: this is temporary solution until JFFS2 driver doesn't have support
for disabling cleanmarker on NAND flash. As JFFS2 driver will have this
feature - this patch could be removed.
Signed-off-by: Arseniy Krasnov <AVKrasnov@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <rockosov@rulkc.org>
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Timings of the nand are adjusted by pl35x_nfc_setup_interface() but
actually applied by the pl35x_nand_select_target() function.
If there is only one nand chip, the pl35x_nand_select_target() will only
apply the timings once since the test at its beginning will always be true
after the first call to this function. As a result, the hardware will
keep using the default timings set at boot to detect the nand chip, not
the optimal ones.
With this patch, we program directly the new timings when
pl35x_nfc_setup_interface() is called.
Fixes: 08d8c62164a3 ("mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller")
Signed-off-by: Olivier Sobrie <olivier@sobrie.be>
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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This helper really is just a little helper for internal purposes, and is
I/O operation oriented, despite its name. It has already been misused
in commit 5008c3ec3f89 ("mtd: spi-nor: core: Check read CR support"), so
rename it to clarify its purpose: it is only useful for reads and page
programs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Commit 5008c3ec3f89 ("mtd: spi-nor: core: Check read CR support") adds a
controller check to make sure the core will not use CR reads on
controllers not supporting them. The approach is valid but the fix is
incorrect. Unfortunately, the author could not catch it, because the
expected behavior was met. The patch indeed drops the RDCR capability,
but it does it for all controllers!
The issue comes from the use of spi_nor_spimem_check_op() which is an
internal helper dedicated to check read/write operations only, despite
its generic name.
This helper looks for the biggest number of address bytes that can be
used for a page operation and tries 4 then 3. It then calls the usual
spi-mem helpers to do the checks. These will always fail because there
is now an inconsistency: the address cycles are forced to 4 (then 3)
bytes, but the bus width during the address cycles rightfully remains
0. There is a non-zero address length but a zero address bus width,
which is an invalid combination.
The correct check in this case is to directly call spi_mem_supports_op()
which doesn't messes up with the operation content.
Fixes: 5008c3ec3f89 ("mtd: spi-nor: core: Check read CR support")
Cc: stable@vger.kernel.org
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Acked-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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When oops_panic_write is set, the driver disables interrupts and
switches to PIO polling mode but still falls through into the DMA
path. DMA cannot be used reliably in panic context, so make the
DMA path an else branch to ensure only PIO is used during panic
writes.
Fixes: c1ac2dc34b51 ("mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling")
Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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nand_lock() and nand_unlock() call into chip->ops.lock_area/unlock_area
without holding the NAND device lock. On controllers that implement
SET_FEATURES via multiple low-level PIO commands, these can race with
concurrent UBI/UBIFS background erase/write operations that hold the
device lock, resulting in cmd_pending conflicts on the NAND controller.
Add nand_get_device()/nand_release_device() around the lock/unlock
operations to serialize them against all other NAND controller access.
Fixes: 92270086b7e5 ("mtd: rawnand: Add support for manufacturer specific lock/unlock operation")
Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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cadence_nand_init()
Fix wrong variable used for error checking after dma_alloc_coherent()
call. The function checks cdns_ctrl->dma_cdma_desc instead of
cdns_ctrl->cdma_desc, which could lead to incorrect error handling.
Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subsystem")
Cc: stable@vger.kernel.org
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Reviewed-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Given CONFIG_FORTIFY_SOURCE=y and a recent compiler,
commit 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when
available") produces the warning below and an oops.
Searching for RedBoot partition table in 50000000.flash at offset 0x7e0000
------------[ cut here ]------------
WARNING: lib/string_helpers.c:1035 at 0xc029e04c, CPU#0: swapper/0/1
memcmp: detected buffer overflow: 15 byte read of buffer size 14
Modules linked in:
CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.19.0 #1 NONE
As Kees said, "'names' is pointing to the final 'namelen' many bytes
of the allocation ... 'namelen' could be basically any length at all.
This fortify warning looks legit to me -- this code used to be reading
beyond the end of the allocation."
Since the size of the dynamic allocation is calculated with strlen()
we can use strcmp() instead of memcmp() and remain within bounds.
Cc: Kees Cook <kees@kernel.org>
Cc: stable@vger.kernel.org
Cc: linux-hardening@vger.kernel.org
Link: https://lore.kernel.org/all/202602151911.AD092DFFCD@keescook/
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Suggested-by: Kees Cook <kees@kernel.org>
Signed-off-by: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Conversion performed via this Coccinelle script:
// SPDX-License-Identifier: GPL-2.0-only
// Options: --include-headers-for-types --all-includes --include-headers --keep-comments
virtual patch
@gfp depends on patch && !(file in "tools") && !(file in "samples")@
identifier ALLOC = {kmalloc_obj,kmalloc_objs,kmalloc_flex,
kzalloc_obj,kzalloc_objs,kzalloc_flex,
kvmalloc_obj,kvmalloc_objs,kvmalloc_flex,
kvzalloc_obj,kvzalloc_objs,kvzalloc_flex};
@@
ALLOC(...
- , GFP_KERNEL
)
$ make coccicheck MODE=patch COCCI=gfp.cocci
Build and boot tested x86_64 with Fedora 42's GCC and Clang:
Linux version 6.19.0+ (user@host) (gcc (GCC) 15.2.1 20260123 (Red Hat 15.2.1-7), GNU ld version 2.44-12.fc42) #1 SMP PREEMPT_DYNAMIC 1970-01-01
Linux version 6.19.0+ (user@host) (clang version 20.1.8 (Fedora 20.1.8-4.fc42), LLD 20.1.8) #1 SMP PREEMPT_DYNAMIC 1970-01-01
Signed-off-by: Kees Cook <kees@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This converts some of the visually simpler cases that have been split
over multiple lines. I only did the ones that are easy to verify the
resulting diff by having just that final GFP_KERNEL argument on the next
line.
Somebody should probably do a proper coccinelle script for this, but for
me the trivial script actually resulted in an assertion failure in the
middle of the script. I probably had made it a bit _too_ trivial.
So after fighting that far a while I decided to just do some of the
syntactically simpler cases with variations of the previous 'sed'
scripts.
The more syntactically complex multi-line cases would mostly really want
whitespace cleanup anyway.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This is the exact same thing as the 'alloc_obj()' version, only much
smaller because there are a lot fewer users of the *alloc_flex()
interface.
As with alloc_obj() version, this was done entirely with mindless brute
force, using the same script, except using 'flex' in the pattern rather
than 'objs*'.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:
Single allocations: kmalloc(sizeof(TYPE), ...)
are replaced with: kmalloc_obj(TYPE, ...)
Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with: kmalloc_objs(TYPE, COUNT, ...)
Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...)
(where TYPE may also be *VAR)
The resulting allocations no longer return "void *", instead returning
"TYPE *".
Signed-off-by: Kees Cook <kees@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD:
- prioritize ofpart in physmap-core probing
- conversions to scoped for each OF child loops
Bindings:
- The bulk of the changes consists of binding fixes/updates to
restrict the use of undefined properties, which was mostly
ineffective in the current form because of the nesting of partition
nodes and the lack of compatible strings
- YAML conversions and the addition of a dma-coherent property in the
cdns,hp-nfc driver
SPI NAND:
- support for octal DTR modes (8D-8D-8D)
- support for Foresee F35SQB002G chips
And small misc fixes"
* tag 'mtd/for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (65 commits)
mtd: spi-nor: hisi-sfc: fix refcounting bug in hisi_spi_nor_register_all()
mtd: spinand: fix NULL pointer dereference in spinand_support_vendor_ops()
mtd: rawnand: pl353: Add message about ECC mode
mtd: rawnand: pl353: Fix software ECC support
mtd: spinand: winbond: Remove unneeded semicolon
dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
mtd: spinand: Disable continuous read during probe
mtd: spinand: add Foresee F35SQB002G flash support
mtd: spinand: winbond: W35N octal DTR support
mtd: spinand: Add octal DTR support
mtd: spinand: Warn if using SSDR-only vendor commands in a non SSDR mode
mtd: spinand: Give the bus interface to the configuration helper
mtd: spinand: Propagate the bus interface across core helpers
mtd: spinand: Add support for setting a bus interface
mtd: spinand: Gather all the bus interface steps in one single function
mtd: spinand: winbond: Configure the IO mode after the dummy cycles
mtd: spinand: winbond: Rename IO_MODE register macro
mtd: spinand: winbond: Fix style
mtd: spinand: winbond: Register W35N vendor specific operation
mtd: spinand: winbond: Register W25N vendor specific operation
...
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SPI NAND
- The major feature this release is the support for octal DTR
modes (8D-8D-8D).
- There has been as well a series of conversion to scoped for each OF
child loops.
- Support for Foresee F35SQB002G chips has been added.
Other changes are small fixes.
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This was converted to a _scoped() loop but this of_node_put() was
accidentally left behind which is a double free.
Fixes: aa8cb72c2018 ("mtd: spi-nor: hisi-sfc: Simplify with scoped for each OF child loop")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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The spinand_support_vendor_ops() helper unconditionally dereferences
info->vendor_ops. For chips that do not define vendor_ops, this pointer
is NULL, leading to a kernel panic during probe:
Unable to handle kernel NULL pointer dereference at virtual address
0000000000000008
Add a guard to return early when vendor_ops is NULL. This prevents the
crash and allows SPI NAND devices without vendor-specific operations to
be probed correctly.
Fixes: fbc7538782f8 ("mtd: spinand: List vendor specific operations and make sure they are supported")
Cc: stable@vger.kernel.org
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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This just add some information on kernel log about the selected ECC
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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We need to set also write_page_raw in ecc structure to allow
choosing SW ECC instead of HW one, otherwise write operation fail.
Fixes: 08d8c62164a322 ("mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller")
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
Cc: stable@kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Remove unnecessary semicolons reported by Coccinelle/coccicheck and the
semantic patch at scripts/coccinelle/misc/semicolon.cocci.
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Macronix serial NAND devices with continuous read support do not
clear the configuration register on soft reset and lack a hardware
reset pin. When continuous read is interrupted (e.g., during reboot),
the feature remains enabled at the device level.
With continuous read enabled, the OOB area becomes inaccessible and
all reads are instead directed to the main area. As a result, during
partition allocation as part of MTD device registration, the first two
bytes of the main area for the master block are read and indicate that
the block is bad. This process repeats for every subsequent block for
the partition.
All reads and writes that reference the BBT find no good blocks and
fail.
The only paths for recovery from this state are triggering the
continuous read feature by way of raw MTD reads or through a NAND
device power drain.
Disable continuous read explicitly during spinand probe to ensure
quiescent feature state.
Fixes: 631cfdd0520d ("mtd: spi-nand: Add continuous read support")
Cc: stable@vger.kernel.org
Signed-off-by: David LaPorte <dalaport@amazon.com>
Reviewed-by: Gunnar Kudrjavets <gunnarku@amazon.com>
Reviewed-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD fix from Miquel Raynal:
"A single late MTD fix, which reverts a fix that turned out to be
incorrect.
The observations of the committer was that the number of IDs to be
used to probe a chip was incorrect. It happened to be a limitation of
his controller, not a chip issue. Restore the chip description, a
solution must be found somewhere else"
* tag 'mtd/fixes-for-6.19-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
Revert "mtd: spinand: esmt: fix id code for F50D1G41LB"
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Add support of Foresee F35SQB002G spinand flash
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Extend the support for the W35N chip family by supporting the ODTR bus
interface. The chip is capable to run in this mode, which brings a
significant performance improvement.
1S-8S-8S:
# flash_speed /dev/mtd0 -c1 -d
eraseblock write speed is 7529 KiB/s
eraseblock read speed is 15058 KiB/s
8D-8D-8D:
# flash_speed /dev/mtd0 -c1 -d
eraseblock write speed is 9481 KiB/s
eraseblock read speed is 23272 KiB/s
This is +55% read speed and +26% write speed with the same hardware.
Tests have been conducted with a TI AM62A7 using the Cadence quad SPI
controller.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Create a new bus interface named ODTR for "octal DTR", which matches the
following pattern: 8D-8D-8D.
Add octal DTR support for all the existing core operations. Add a second
set of templates for this bus interface.
Give the possibility for drivers to register their read, write and
update cache variants as well as their vendor specific operations.
Check the SPI controller driver supports all the octal DTR commands that
we might need before switching to the ODTR bus interface.
Make the switch by calling ->configure_chip() with the ODTR
parameter. Fallback in case this step fails.
If someone ever attempts to suspend a chip in octal DTR mode, there are
changes that it will loose its configuration at resume. Prevent any
problem by explicitly switching back to SSDR while suspending. Note:
there is a limitation in the current approach, page I/Os are not
available as the dirmaps will be created for the ODTR bus interface if
that option is supported and not switched back to SSDR during
suspend. Switching them is possible but would be costly and would not
bring anything as right after resuming we will switch again to ODTR. In
case this capability is used for debug, developpers should mind to
destroy and recreate suitable direct mappings.
Finally, as a side effect, we increase the buffer for reading IDs to
6. No device at this point returns 6 bytes, but we support 5 bytes IDs,
which means in octal DTR mode we have no other choice than reading an
even number of bytes, hence 6.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Both Macronix and Winbond have chip specific operations which are SSDR
only. Trying to use them in an ODTR setup will fail and doing this is a
pure software bug. Warn explicitly in this case.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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The chip configuration hook is the one responsible to actually switch
the switch between bus interfaces. It is natural to give it the bus
interface we expect with a new parameter. For now the only value we can
give is SSDR, but this is subject to change in the future, so add a bit
of extra logic in the implementations of this callback to make sure
both the core and the chip driver are aligned on the request.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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For now all drivers provide SSDR variants only. When we add support for
ODTR modes, there will be a need to differentiate the type of variant we
target as well as the need to check if we support one or the other type
of operations.
Pass this parameter to lower level helpers, which for now is unused, in
order to simplify the patch introducing ODTR support.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Create a bus interface enumeration, currently only containing the
one we support: SSDR, for single SDR, so any operation whose command is
sent over a single data line in SDR mode, ie. any operation matching
1S-XX-XX.
The main spinand_device structure gets a new parameter to store this
enumeration, for now unused. Of course it is set to SSDR during the SSDR
templates initialization to further clarify the state we are in at the
moment.
This member is subject to be used to know in which bus configuration we
and be updated by the core when we switch to faster mode(s).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Writing the quad enable bit in one helper and doing the chip
configuration in another does not make much sense from a bus interface
setup point of view.
Instead, let's create a broader helper which is going to be in charge of
all the bus configuration steps at once. This will specifically allow to
transition to octal DDR mode, and even fallback to quad (if suppoorted)
or single mode otherwise.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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When we will change the bus interface, the action that actually performs
the transition is the IO mode register write. This means after the IO
mode register write, we should use the new bus interface. But the
->configure_chip() hook itself is not responsible of making this change
official, it is the caller that must act according to the return value.
Reorganize this helper to first configure the dummy cycles before
possibly switching to another bus interface.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Suffix the macro name with *_REG to align with the rest of the driver.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Add a missing new line in the middle of the driver.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Provide the Winbond W35N specific "write VCR register" operation to let
the core verify it is supported by the controller before using it.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Provide the Winbond W25N specific "select target" operation to let the
core verify it is supported by the controller before using it.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Provide the Macronix specific "read ECC status register" operation so
that the core can verify if it is supported by the controller before
using it.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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It is probably safe to expect that all SPI controller drivers will ever
support all the most basic SPI NAND operations, such as write enable,
register reads, page program, block erases, etc. However, what about
vendor specific operations? So far nobody complained about it, but as we
are about to introduce octal DTR support, and as none of the SPI NAND
instruction set is defined in any standard, we must remain careful about
these extra operations.
One way to make sure we do not blindly get ourselves in strange
situations with vendor commands failing silently is to make the check
once for all, while probing the chip. However at this stage we have no
such list, so let's add the necessary infrastructure to allow:
- registering vendor operations,
- checking they are actually supported when appropriate.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Winbond W35N* chips require a vendor specific operation to write their
VCR register (a configuration register, typically used for tuning the
number of dummy cycles and switching to a different bus
interface). Instead of defining this op only in the function that needs
it, hiding it from the core, make it a proper define like all other
spi-mem operations, and implement the necessary spinand_fill_*_op()
helper to make the SPINAND_OP() macro work. This way we can use it from
any function without any extra handling outside of this helper when we
will convert the core to support octal DDR busses.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Winbond W25N* chips require a vendor specific operation to select the
target. Instead of defining this op only in the function that
needs it, hiding it from the core, make it a proper define like all
other spi-mem operations, and implement the necessary
spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way
we can use it from any function without any extra handling outside of
this helper when we will convert the core to support octal DDR busses.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Macronix chips require a vendor specific operation to read the ECC
status register. Instead of defining this op only in the function that
needs it, hiding it from the core, make it a proper define like all
other spi-mem operations, and implement the necessary
spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way
we can use it from any function without any extra handling outside of
this helper when we will convert the core to support octal DDR busses.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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