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| author | Jesse Zhang <Jesse.Zhang@amd.com> | 2026-09-03 17:36:21 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-09-10 12:08:18 -0400 |
| commit | 17bd3e9f404ec18924a330b9ebb3281711ea6580 (patch) | |
| tree | 5fe5809f56011719ac4ad34785a52b22cfd269af | |
| parent | cf8112f6714eb3b955cf663371ce44b70a1d220d (diff) | |
| download | linux-next-17bd3e9f404ec18924a330b9ebb3281711ea6580.tar.gz linux-next-17bd3e9f404ec18924a330b9ebb3281711ea6580.zip | |
drm/amdgpu/sdma6: implement detect_hung_queue
Match each SDMA queue's DOORBELL_OFFSET register against the given
doorbell to recover its (instance, queue_id) HW slot. The per-queue
register stride is derived from the named QUEUE0/QUEUE1 registers.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 303fd7d1b7c8..0b64eb5b32e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1556,6 +1556,34 @@ static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) return r; } +/* dword stride between adjacent per-queue register banks */ +#define SDMA_V6_0_QUEUE_REG_STRIDE \ + (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL) + +/* find the HW slot (instance, queue_id) whose doorbell matches doorbell_index */ +static bool sdma_v6_0_detect_hung_queue(struct amdgpu_device *adev, + u32 doorbell_index, + u32 *instance_id, u32 *queue_id) +{ + u32 i, q, reg, dboff; + + for (i = 0; i < adev->sdma.num_instances; i++) { + for (q = 0; q < 8; q++) { + reg = sdma_v6_0_get_reg_offset(adev, i, + regSDMA0_QUEUE0_DOORBELL_OFFSET + + q * SDMA_V6_0_QUEUE_REG_STRIDE); + dboff = (RREG32(reg) & + SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK) >> 2; + if (dboff == doorbell_index) { + *instance_id = i; + *queue_id = q; + return true; + } + } + } + return false; +} + static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -1762,6 +1790,10 @@ static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { .reset = sdma_v6_0_reset_queue, }; +static const struct amdgpu_sdma_funcs sdma_v6_0_sdma_funcs = { + .detect_hung_queue = sdma_v6_0_detect_hung_queue, +}; + static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) { int i; @@ -1769,6 +1801,7 @@ static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) for (i = 0; i < adev->sdma.num_instances; i++) { adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; adev->sdma.instance[i].ring.me = i; + adev->sdma.instance[i].funcs = &sdma_v6_0_sdma_funcs; } } |
