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| author | Ashish Mhetre <amhetre@nvidia.com> | 2026-06-22 06:54:09 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-07-26 13:48:38 +0000 |
| commit | 20df8037968d3c088e507586bcac44b51aae3cbd (patch) | |
| tree | eafd3aa2d81f22e94b8dafed8efc0cc2f21a4de5 | |
| parent | 7b97226bfb4ff96ecff7408160e8e50a5d70e48b (diff) | |
| download | linux-next-20df8037968d3c088e507586bcac44b51aae3cbd.tar.gz linux-next-20df8037968d3c088e507586bcac44b51aae3cbd.zip | |
dt-bindings: iommu: Fix interrupt type in example
The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
interrupt documentation, but the binding example describes it as
level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
that it does not propagate the wrong trigger type.
Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; }; |