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| author | Pranay Samala <pranay.samala@intel.com> | 2026-09-02 13:24:14 +0530 |
|---|---|---|
| committer | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2026-09-15 12:24:51 +0530 |
| commit | 2a8563b84c806ef4b2f919b09089e10a92da447c (patch) | |
| tree | b69784e4dd6c44ef7a38a6b782dc6b4afc311b81 | |
| parent | 8249ceb6bb4c05825517d13eca28a5b572350946 (diff) | |
| download | linux-next-2a8563b84c806ef4b2f919b09089e10a92da447c.tar.gz linux-next-2a8563b84c806ef4b2f919b09089e10a92da447c.zip | |
drm/i915/color: Extract HDR post-CSC LUT programming to helper function
Move HDR plane post-CSC LUT programming to improve code organization.
While at it, remove the segment 0 index register writes as it is not
currently programmed.
Signed-off-by: Pranay Samala <pranay.samala@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260902075417.656673-7-chaitanya.kumar.borah@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_color.c | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 87ced9f6ff40..36c8688ed28e 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3998,25 +3998,17 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, } static void -xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, - const struct intel_plane_state *plane_state) +xelpd_load_hdr_post_csc_lut(struct intel_display *display, + struct intel_dsb *dsb, + enum pipe pipe, + enum plane_id plane, + const struct drm_color_lut32 *post_csc_lut) { - struct intel_display *display = to_intel_display(plane_state); - const struct drm_plane_state *state = &plane_state->uapi; - enum pipe pipe = to_intel_plane(state->plane)->pipe; - enum plane_id plane = to_intel_plane(state->plane)->id; - const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data; int i, lut_size = 32; u32 lut_val; - if (!icl_is_hdr_plane(display, plane)) - return; - intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), PLANE_PAL_PREC_AUTO_INCREMENT); - /* TODO: Add macro */ - intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), - PLANE_PAL_PREC_AUTO_INCREMENT); for (i = 0; i < lut_size + 3; i++) { if (post_csc_lut) { @@ -4036,8 +4028,21 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, } intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); - intel_de_write_dsb(display, dsb, - PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0); +} + +static void +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, + const struct intel_plane_state *plane_state) +{ + struct intel_display *display = to_intel_display(plane_state); + const struct drm_plane_state *state = &plane_state->uapi; + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut ? + plane_state->hw.gamma_lut->data : NULL; + + if (icl_is_hdr_plane(display, plane)) + xelpd_load_hdr_post_csc_lut(display, dsb, pipe, plane, post_csc_lut); } static void |