diff options
| author | Jia Wang <wangjia@ultrarisc.com> | 2026-09-02 17:26:13 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-09-10 19:27:22 +0530 |
| commit | 2a9013c20c46216b92ff09e2283b5244a91c59da (patch) | |
| tree | cea6255e80f82caf413c7c0f77f44b4e4f345a7a | |
| parent | e6b49f8016ee8b642e8e495d1704342ee0b35d72 (diff) | |
| download | linux-next-2a9013c20c46216b92ff09e2283b5244a91c59da.tar.gz linux-next-2a9013c20c46216b92ff09e2283b5244a91c59da.zip | |
dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position
The CH_CFG2 channel priority field occupies bits 51:47 of the 64-bit
channel configuration register, corresponding to bits 19:15 of CH_CFG2_H.
The driver currently shifts the priority value by 20, programming the
wrong bits. Use bit 15 as the field position.
Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260902-dma-fix-v3-3-414c6449fbcc@ultrarisc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index 039316c42f05..da706bff3f12 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -326,7 +326,7 @@ enum { #define CH_CFG2_H_TT_FC_POS 0 #define CH_CFG2_H_HS_SEL_SRC_POS 3 #define CH_CFG2_H_HS_SEL_DST_POS 4 -#define CH_CFG2_H_PRIORITY_POS 20 +#define CH_CFG2_H_PRIORITY_POS 15 /** * DW AXI DMA channel interrupts |