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| author | Maxime Chevallier <maxime.chevallier@bootlin.com> | 2026-08-31 09:01:19 +0200 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2026-09-03 10:31:34 +0200 |
| commit | 384ee2379a66a86903e1acccc30c2f87a3020809 (patch) | |
| tree | 581c6127980ce19cb73eaf6eb0a140573b6f790a | |
| parent | e16acadb9a0f7a0f04318e4b3a8e89e8ddd0c905 (diff) | |
| download | linux-next-384ee2379a66a86903e1acccc30c2f87a3020809.tar.gz linux-next-384ee2379a66a86903e1acccc30c2f87a3020809.zip | |
net: stmmac: dwmac4: Read the UC filter size from hardware capabilities
dwmac4 has multiple banks of perfect filter entries, independently
configurable during IP integration.
The multi_addr bank reports a number between 0 and 31 corresponding to
the actual number of entries in that bank, while the 32 and 64 banks
are all-or-nothing.
Expose these caps over debugfs as well.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Nicolai Buchwitz <nb@tipi-net.de>
Link: https://patch.msgid.link/20260831070121.349778-2-maxime.chevallier@bootlin.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/common.h | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 4 | ||||
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 |
4 files changed, 19 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 927ea6230073..77bd47a83357 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -419,6 +419,8 @@ struct dma_features { unsigned int half_duplex; unsigned int hash_filter; unsigned int multi_addr; + unsigned int additional_32_addr; + unsigned int additional_64_addr; unsigned int pcs; unsigned int sma_mdio; unsigned int pmt_remote_wake_up; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 6382836828ba..89368e34a388 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -176,7 +176,9 @@ enum power_event { /* MAC HW features0 bitmap */ #define GMAC_HW_FEAT_SAVLANINS BIT(27) -#define GMAC_HW_FEAT_ADDMAC BIT(18) +#define GMAC_HW_FEAT_MACADR64SEL BIT(24) +#define GMAC_HW_FEAT_MACADR32SEL BIT(23) +#define GMAC_HW_FEAT_ADDMAC GENMASK(22, 18) #define GMAC_HW_FEAT_RXCOESEL BIT(16) #define GMAC_HW_FEAT_TXCOSEL BIT(14) #define GMAC_HW_FEAT_EEESEL BIT(13) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 23ffe1adcd0d..14ac3f0e51f7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -388,6 +388,8 @@ static int dwmac4_get_hw_feature(void __iomem *ioaddr, dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; + dma_cap->additional_32_addr = (hw_cap & GMAC_HW_FEAT_MACADR32SEL) >> 23; + dma_cap->additional_64_addr = (hw_cap & GMAC_HW_FEAT_MACADR64SEL) >> 24; dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 66ae365e1c89..30a539b100f8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -6582,6 +6582,18 @@ static int stmmac_dma_cap_show(struct seq_file *seq, void *v) seq_printf(seq, "\tNumber of Additional MAC address registers: %d\n", priv->dma_cap.multi_addr); + } else if (priv->plat->core_type == DWMAC_CORE_GMAC4) { + seq_printf(seq, + "\tNumber of MAC address registers (1-31): %d\n", + priv->dma_cap.multi_addr); + seq_printf(seq, + "\tAdditional 32 MAC address registers (32-63): %s\n", + priv->dma_cap.additional_32_addr ? "Y" : "N"); + seq_printf(seq, + "\tAdditional 64 MAC address registers (64-127): %s\n", + priv->dma_cap.additional_64_addr ? "Y" : "N"); + seq_printf(seq, "\tHash Filter: %s\n", + (priv->dma_cap.hash_filter) ? "Y" : "N"); } else { seq_printf(seq, "\tHash Filter: %s\n", (priv->dma_cap.hash_filter) ? "Y" : "N"); |