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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-06-10 17:09:54 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-07-31 17:40:09 +0200 |
| commit | 3f856cf050cb45e5921ebabf32ecde4f135c04e9 (patch) | |
| tree | db07f5bb51bdd23d097d7a878def36b3a1ccfc45 | |
| parent | 30a140dabeb20eea38c183da5fef764a9442e309 (diff) | |
| download | linux-next-3f856cf050cb45e5921ebabf32ecde4f135c04e9.tar.gz linux-next-3f856cf050cb45e5921ebabf32ecde4f135c04e9.zip | |
arm64: tegra: Drop CPU masks from GICv3 PPI interrupts
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 820670dd6042..ffdaf9d8d947 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4083,7 +4083,7 @@ reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent = <&gic>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #redistributor-regions = <1>; #interrupt-cells = <3>; @@ -5885,10 +5885,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gic>; always-on; }; |