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authorMiquel Raynal <miquel.raynal@bootlin.com>2026-09-04 19:19:19 +0200
committerMichael Walle <mwalle@kernel.org>2026-09-07 09:45:07 +0200
commit41d96c2da5970f7e25b7818710d7732f5035cdb4 (patch)
tree950b4272793d97cc8bdba808c09fc2182f2c574a
parent6648e64c6efe6a0b11a080ef1a87e26147085774 (diff)
downloadlinux-next-41d96c2da5970f7e25b7818710d7732f5035cdb4.tar.gz
linux-next-41d96c2da5970f7e25b7818710d7732f5035cdb4.zip
mtd: spi-nor: winbond: W25Q01JV-M: New chip
Add support for W25Q01JV-M. It is a 3.3V chip with usual dual/quad capabilities. The SFDP table is pretty complete except for the locking capabilities which must be filled manually. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Walle <mwalle@kernel.org>
-rw-r--r--drivers/mtd/spi-nor/winbond.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 5b81de305d8e..f59587b859a9 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -341,6 +341,12 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
+ /* W25Q01JV-M */
+ .id = SNOR_ID(0xef, 0x70, 0x21),
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+ SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
+ .fixups = &winbond_nor_multi_die_fixups,
+ }, {
/* W25Q02JV-M */
.id = SNOR_ID(0xef, 0x70, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |