soc: fsl: qe: Fix sparse warnings in GPIO

A C=2 build on mpc83xx_defconfig provides following warnings:

  drivers/soc/fsl/qe/gpio.c:44:34: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:44:34:    expected restricted __be32 [usertype] cpdata
  drivers/soc/fsl/qe/gpio.c:44:34:    got unsigned int [usertype] cpdata
  drivers/soc/fsl/qe/gpio.c:45:34: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:45:34:    expected restricted __be32 [usertype] cpdir1
  drivers/soc/fsl/qe/gpio.c:45:34:    got unsigned int
  drivers/soc/fsl/qe/gpio.c:46:34: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:46:34:    expected restricted __be32 [usertype] cpdir2
  drivers/soc/fsl/qe/gpio.c:46:34:    got unsigned int
  drivers/soc/fsl/qe/gpio.c:47:34: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:47:34:    expected restricted __be32 [usertype] cppar1
  drivers/soc/fsl/qe/gpio.c:47:34:    got unsigned int
  drivers/soc/fsl/qe/gpio.c:48:34: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:48:34:    expected restricted __be32 [usertype] cppar2
  drivers/soc/fsl/qe/gpio.c:48:34:    got unsigned int
  drivers/soc/fsl/qe/gpio.c:49:33: warning: incorrect type in assignment (different base types)
  drivers/soc/fsl/qe/gpio.c:49:33:    expected restricted __be32 [usertype] cpodr
  drivers/soc/fsl/qe/gpio.c:49:33:    got unsigned int
  drivers/soc/fsl/qe/gpio.c:297:17: warning: restricted __be32 degrades to integer
  drivers/soc/fsl/qe/gpio.c:299:17: warning: restricted __be32 degrades to integer
  drivers/soc/fsl/qe/gpio.c:302:17: warning: restricted __be32 degrades to integer
  drivers/soc/fsl/qe/gpio.c:304:17: warning: restricted __be32 degrades to integer
  drivers/soc/fsl/qe/gpio.c:308:18: warning: restricted __be32 degrades to integer
  drivers/soc/fsl/qe/gpio.c:314:9: warning: restricted __be32 degrades to integer

The problem is the 'struct qe_pio_reg' embedded in 'struct qe_gpio_chip'
to save register values. As the values are read with ioread32be(), they
are now in CPU byte order and can't be stored as-is in a __be32 object.

Replace 'struct qe_pio_reg saved_regs' by individual u32 fields.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202608051952.ADkLIB86-lkp@intel.com/
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202608130908.gEy44F1D-lkp@intel.com/
Link: https://lore.kernel.org/r/6a84b38e766729676b375c93bf54c67ea455288d.1786080840.git.chleroy@kernel.org
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>

1 files changed, 19 insertions, 19 deletions

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 5cd59cfbf22f..8e210f8a3b6c 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -32,8 +32,13 @@ struct qe_gpio_chip {
 	/* shadowed data register to clear/set bits safely */
 	u32 cpdata;
 
-	/* saved_regs used to restore dedicated functions */
-	struct qe_pio_regs saved_regs;
+	/* saved regs used to restore dedicated functions */
+	u32 saved_cpodr;
+	u32 saved_cpdata;
+	u32 saved_cpdir1;
+	u32 saved_cpdir2;
+	u32 saved_cppar1;
+	u32 saved_cppar2;
 };
 
 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
@@ -41,12 +46,12 @@ static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
 	struct qe_pio_regs __iomem *regs = qe_gc->regs;
 
 	qe_gc->cpdata = ioread32be(&regs->cpdata);
-	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
-	qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
-	qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
-	qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
-	qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
-	qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
+	qe_gc->saved_cpdata = qe_gc->cpdata;
+	qe_gc->saved_cpdir1 = ioread32be(&regs->cpdir1);
+	qe_gc->saved_cpdir2 = ioread32be(&regs->cpdir2);
+	qe_gc->saved_cppar1 = ioread32be(&regs->cppar1);
+	qe_gc->saved_cppar2 = ioread32be(&regs->cppar2);
+	qe_gc->saved_cpodr = ioread32be(&regs->cpodr);
 }
 
 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -284,7 +289,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
 {
 	struct qe_gpio_chip *qe_gc = qe_pin->controller;
 	struct qe_pio_regs __iomem *regs = qe_gc->regs;
-	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
 	int pin = qe_pin->num;
 	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
 	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
@@ -294,24 +298,20 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
 	spin_lock_irqsave(&qe_gc->lock, flags);
 
 	if (second_reg) {
-		qe_clrsetbits_be32(&regs->cpdir2, mask2,
-				   sregs->cpdir2 & mask2);
-		qe_clrsetbits_be32(&regs->cppar2, mask2,
-				   sregs->cppar2 & mask2);
+		qe_clrsetbits_be32(&regs->cpdir2, mask2, qe_gc->saved_cpdir2 & mask2);
+		qe_clrsetbits_be32(&regs->cppar2, mask2, qe_gc->saved_cppar2 & mask2);
 	} else {
-		qe_clrsetbits_be32(&regs->cpdir1, mask2,
-				   sregs->cpdir1 & mask2);
-		qe_clrsetbits_be32(&regs->cppar1, mask2,
-				   sregs->cppar1 & mask2);
+		qe_clrsetbits_be32(&regs->cpdir1, mask2, qe_gc->saved_cpdir1 & mask2);
+		qe_clrsetbits_be32(&regs->cppar1, mask2, qe_gc->saved_cppar1 & mask2);
 	}
 
-	if (sregs->cpdata & mask1)
+	if (qe_gc->saved_cpdata & mask1)
 		qe_gc->cpdata |= mask1;
 	else
 		qe_gc->cpdata &= ~mask1;
 
 	iowrite32be(qe_gc->cpdata, &regs->cpdata);
-	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
+	qe_clrsetbits_be32(&regs->cpodr, mask1, qe_gc->saved_cpodr & mask1);
 	spin_unlock_irqrestore(&qe_gc->lock, flags);
 }
 EXPORT_SYMBOL(qe_pin_set_dedicated);