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| author | Ashish Mhetre <amhetre@nvidia.com> | 2026-06-22 06:54:10 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-07-31 17:38:20 +0200 |
| commit | 5af7a8a522f61ae2a3e5038c889e231e56d63526 (patch) | |
| tree | 3e000468e86c2202ac45cc57a7f3f89b314a43c7 | |
| parent | 96c5696a58fa527873c261f74d74f81303e756fe (diff) | |
| download | linux-next-5af7a8a522f61ae2a3e5038c889e231e56d63526.tar.gz linux-next-5af7a8a522f61ae2a3e5038c889e231e56d63526.zip | |
arm64: tegra: Fix CMDQV interrupt type on Tegra264
The CMDQV interrupts on Tegra264 are described as level-triggered, but
per the hardware interrupt documentation these interrupts are actually
edge-triggered.
Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH
to IRQ_TYPE_EDGE_RISING.
Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra264.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 42b143155ed4..4073e3905f81 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3413,7 +3413,7 @@ cmdqv1: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x5200000 0x0 0x830000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; @@ -3433,7 +3433,7 @@ cmdqv2: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; @@ -3506,7 +3506,7 @@ cmdqv0: cmdqv@a200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xa200000 0x0 0x830000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; @@ -3526,7 +3526,7 @@ cmdqv4: cmdqv@b200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xb200000 0x0 0x830000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; @@ -3914,7 +3914,7 @@ cmdqv3: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; |