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| author | Jared McArthur <j-mcarthur@ti.com> | 2026-09-08 13:59:03 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2026-09-11 14:47:56 -0500 |
| commit | 7e4b4f799bd043cb5b30176ddbe690a0fb5788bc (patch) | |
| tree | 6c4930e4f3fc7c5c0f7adda469b76f4255ab5850 | |
| parent | 02b57c8a48ecbf5e1c11a62da840b4ae7e6332a6 (diff) | |
| download | linux-next-7e4b4f799bd043cb5b30176ddbe690a0fb5788bc.tar.gz linux-next-7e4b4f799bd043cb5b30176ddbe690a0fb5788bc.zip | |
arm64: dts: ti: k3-j784s4-j742s2-evm-common: Set ACSPCIe refclk to MAIN_PLL2_HSDIV4 for pcie1
Commit e3dfcf482d07 ("arm64: dts: ti: k3-j784s4-j742s2-evm-common:
Enable ACSPCIE0 output for PCIe1") enabled the ACSPCIE0 buffers
to provide the PCIe refclk for PCIe1, but introduced a bug
where the clock is remporarily disabled during initialization.
The ACSPCIe reference clock is muxable between multiple
sources: SERDESx_REF_DER_OUT_CLK, MAIN_PLL2_HSDIV4_CLKOUT, and
SERDESx_REF_OUT_CLK [0]. On reset, the refclk is set to the
SERDESx_REF_DER_OUT_CLK. In the J742S2 and J784S4, "the SerDes PCIe
Reference Clock Output will be temporarily disabled when changing Data
Rates to or from 8.0 GT/s in Derived Refclk mode" [1]. Some external PCIe
devices cannot tolerate the reference clock being disabled and will
therefore fail to link.
This advisory is described in more detail as: i2242 of the J784S4
Silicon Revision 1.0 (Rev. B) document [1].
The refclk for devices connected to PCIe1 is provided by the ACSPCIe
buffers in the J742S2XH01EVM [2] and J784S4XEVM [3]. Work around
the advisory by setting the ACSPCIe reference clock source to
MAIN_PLL2_HSDIV4_CLKOUT. Use the TI SCI clock controller to assign the
clock's source [4].
[0] https://www.ti.com/lit/zip/spruj52
[1] https://www.ti.com/lit/pdf/SPRZ536
[2] https://www.ti.com/lit/zip/SPAC001
[3] https://www.ti.com/lit/zip/SPRR458
[4] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html
Fixes: e3dfcf482d07 ("arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1")
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://patch.msgid.link/20260908185903.404451-1-j-mcarthur@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index ff3a85cbc524..7c085663c888 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -1206,6 +1206,8 @@ status = "okay"; clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; clock-names = "fck", "pcie_refclk"; + assigned-clocks = <&k3_clks 415 0>; + assigned-clock-parents = <&k3_clks 415 2>; num-lanes = <2>; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie1_link>; |