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| author | Nikita Travkin <nikita@trvn.ru> | 2025-05-03 15:39:29 +0500 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-05-06 22:26:35 -0700 |
| commit | 8a401135001c65203f3fd210d482bc7eae1bfc56 (patch) | |
| tree | dcdba47eb1cfc15cd1a651bc9c1fd51ae09e27eb | |
| parent | 0d95f64be4176fc98bcc2b4558239800ee93bf32 (diff) | |
| download | linux-next-8a401135001c65203f3fd210d482bc7eae1bfc56.tar.gz linux-next-8a401135001c65203f3fd210d482bc7eae1bfc56.zip | |
arm64: dts: qcom: sc8280xp: Add PCIe IOMMU
sc8280xp has an SMMUv3 connected to PCIe which is normally controlled by
QHEE and is thus transparent to the OS. However if we boot Linux in EL2,
without QHEE, we need to manage this IOMMU ourselves. To make that
easier, and since the hardware actually exists, just not "usually"
managed by Linux, describe it in the dts as "reserved".
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-2-24e9b4572e15@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 35ef31d4ecf2..27d21e1a2d50 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4927,6 +4927,20 @@ }; }; + pcie_smmu: iommu@14f80000 { + compatible = "arm,smmu-v3"; + reg = <0 0x14f80000 0 0x80000>; + #iommu-cells = <1>; + interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by QHEE. */ + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; |