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| author | Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> | 2026-07-13 14:58:38 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-07-29 16:15:06 -0500 |
| commit | a3ba349af8e1bb7e0efdcd2dd53d69282f18478a (patch) | |
| tree | 44d8a1b1133cf0e26a509bc449fd04c8e2b54688 | |
| parent | 07db10de262f4150e24fd631a7a6c428f7bf80c9 (diff) | |
| download | linux-next-a3ba349af8e1bb7e0efdcd2dd53d69282f18478a.tar.gz linux-next-a3ba349af8e1bb7e0efdcd2dd53d69282f18478a.zip | |
arm64: dts: qcom: eliza: Fix DSI1 phy reference clock rate
The DSI PHY CXO clock input is the SoC CXO divided by two. DSI0 already
uses correct one, but DSI1 got copy-paste from SM8750, which had same
problem and copy-pasted code from SM8650. Wrong clock parent will cause
incorrect DSI1 PHY PLL frequencies to be used making the DSI panel
non-working, although there is no upstream user of DSI1.
Fixes: 159d252ed800 ("arm64: dts: qcom: eliza: Add display (MDSS) with Display CC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260713125837.727632-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/eliza.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 977de44b816e..72b786fec195 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2559,7 +2559,7 @@ "dsi_pll"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "ref"; |