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| author | Nick Chan <towinchenmi@gmail.com> | 2025-02-20 20:21:45 +0800 |
|---|---|---|
| committer | Sven Peter <sven@svenpeter.dev> | 2025-04-13 12:46:30 +0200 |
| commit | a7a38536f2ea5d3797b9d647d4a8abdaa36ebeb3 (patch) | |
| tree | 136cddff3367e2eb22438b07f2996ca130ebdfb5 | |
| parent | 93669da1d1e35cb8d4df7e7f9765721c998521e7 (diff) | |
| download | linux-next-a7a38536f2ea5d3797b9d647d4a8abdaa36ebeb3.tar.gz linux-next-a7a38536f2ea5d3797b9d647d4a8abdaa36ebeb3.zip | |
arm64: dts: apple: s800-0-3: Add CPU caches
Add information about CPU caches in both variants of Apple A9 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-4-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
| -rw-r--r-- | arch/arm64/boot/dts/apple/s800-0-3.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index c0e9ae45627c..09db4ed64054 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -36,6 +36,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -46,6 +49,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; }; }; |