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| author | Alex Elder <elder@riscstar.com> | 2026-09-02 16:43:16 -0500 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-09-03 09:40:12 -0500 |
| commit | aaedd4ea312d6fd70dfc5cf430edf5106c5b3382 (patch) | |
| tree | 1bf85ff6887384d90885c7e9ab02ffef2f7b5c63 | |
| parent | df4107fc729e3bffce27fe0ed06fc6a64dd675cd (diff) | |
| download | linux-next-aaedd4ea312d6fd70dfc5cf430edf5106c5b3382.tar.gz linux-next-aaedd4ea312d6fd70dfc5cf430edf5106c5b3382.zip | |
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes
The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes
representing TC956x chips, each of which contains a PCIe switch and
an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property
for the two PCIe functions. That property should only be used for a
PCI device "that implements a PCI bus". Remove this property for the
two function nodes.
In addition, only PCI bridge nodes should be named "pcie@" (or "pci@").
PCI endpoint nodes are typically named based on the functionality they
implement (e.g., "ethernet@"). In this case, the role of these PCI
functions is not (yet) specified, and furthermore they will be used
with PCI endpoint buses. Rename these to use "dev@", following the
convention used in of_pci_make_dev_node() for dynamically-created
devicetree nodes.
Finally, these nodes define #address-cells, #size-cells, and ranges
properties, which are not normally defined for PCIe endpoints. Remove
these properties as well; they can be added back once they are actually
needed/used.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Fixes: 4559b435f741b ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0")
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20260902214321.1721477-3-elder@riscstar.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 46bb52c667a4..5259f4f4f857 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,20 +130,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; @@ -225,20 +217,12 @@ ranges; bus-range = <0x5 0xff>; - pcie@0,0 { + dev@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; - pcie@0,1 { + dev@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; }; |