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authorBalakrishnan Sambath <balakrishnan.s@microchip.com>2026-08-17 12:22:06 +0530
committerHans Verkuil <hverkuil+cisco@kernel.org>2026-09-09 09:16:32 +0200
commitbb96c78c5f87072913f8825faebe64bf711a503c (patch)
tree223d23b84ace5c27b940e3dbab2a9f5c13f9061e
parent21ad8225822a892c4c273bf1368d477a83a19dbb (diff)
downloadlinux-next-bb96c78c5f87072913f8825faebe64bf711a503c.tar.gz
linux-next-bb96c78c5f87072913f8825faebe64bf711a503c.zip
media: microchip-isc: fix SBGGR10 Bayer pattern
SBGGR10 was mapped to ISC_BAY_CFG_RGRG instead of ISC_BAY_CFG_BGBG, causing red/blue channel swap. Fixes: 1e8f401474d6 ("media: atmel: atmel-isc: reworked driver and formats") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath <balakrishnan.s@microchip.com> Reviewed-by: Eugen Hristev <ehristev@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
-rw-r--r--drivers/media/platform/microchip/microchip-sama5d2-isc.c2
-rw-r--r--drivers/media/platform/microchip/microchip-sama7g5-isc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/drivers/media/platform/microchip/microchip-sama5d2-isc.c
index 57a5aae3cabf..5e41eee45dbd 100644
--- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c
+++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c
@@ -148,7 +148,7 @@ static struct isc_format sama5d2_formats_list[] = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_TEN,
- .cfa_baycfg = ISC_BAY_CFG_RGRG,
+ .cfa_baycfg = ISC_BAY_CFG_BGBG,
},
{
.fourcc = V4L2_PIX_FMT_SGBRG10,
diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/drivers/media/platform/microchip/microchip-sama7g5-isc.c
index a841266ffc30..9e78ea07b013 100644
--- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c
+++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c
@@ -157,7 +157,7 @@ static struct isc_format sama7g5_formats_list[] = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_TEN,
- .cfa_baycfg = ISC_BAY_CFG_RGRG,
+ .cfa_baycfg = ISC_BAY_CFG_BGBG,
},
{
.fourcc = V4L2_PIX_FMT_SGBRG10,