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| author | Randy Dunlap <rdunlap@infradead.org> | 2026-07-26 17:10:02 -0700 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-07-28 10:28:33 +0000 |
| commit | d50a908ffde534596107072c4897cf17c5ccd9e5 (patch) | |
| tree | 28b452ce01efc5fd11fcae416cc4a27c1d45c0b5 | |
| parent | bc7f7ddc64df4b821d7dce97db58c5bf84e0efd1 (diff) | |
| download | linux-next-d50a908ffde534596107072c4897cf17c5ccd9e5.tar.gz linux-next-d50a908ffde534596107072c4897cf17c5ccd9e5.zip | |
arm64: fix cpu-feature-registers Malformed table
The "visible" column was dropped so that last line's extra pieces
should also be dropped to prevent a docs build error:
Documentation/arch/arm64/cpu-feature-registers.rst:170: ERROR: Malformed table.
Right border not aligned or missing.
+------------------------------+---------+
| Name | bits |
+------------------------------+---------+
| RNDR | [63-60] |
+------------------------------+---------+
| TS | [55-52] |
+------------------------------+---------+
...
+------------------------------+---------+
| AES | [7-4] |
+------------------------------+---------+---------+ [docutils]
Fixes: bc7f7ddc64df ("arm64: Remove hidden bitfields from cpu-feature-registers.rst")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/arch/arm64/cpu-feature-registers.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst index fc63ccb666bf..f603afe323d6 100644 --- a/Documentation/arch/arm64/cpu-feature-registers.rst +++ b/Documentation/arch/arm64/cpu-feature-registers.rst @@ -167,7 +167,7 @@ infrastructure: | SHA1 | [11-8] | +------------------------------+---------+ | AES | [7-4] | - +------------------------------+---------+---------+ + +------------------------------+---------+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1 |