Merge branch 'for-next/cpufeature' into for-next/core

* for-next/cpufeature:
  arm64: bti: Disable in-kernel BTI with recent versions of Clang
  iommu/arm-smmu-v3-sva: Use system_supports_bbml3() to detect CPU feature
  arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM
  arm64: cpufeature: Rename BBML2_NOABORT as BBML3
  arm64: sysreg: Add BBM_3
  arm64: cpufeature: Extend bbml2_noabort support list
  arm64: cputype: Add C1-Nano definitions
  arm64: cputype: Add Cortex-A520AE definitions
  arm64: cpucaps: Remove stale comment about keeping capabilities sorted
  arm64: fix cpu-feature-registers Malformed table
  arm64: Remove hidden bitfields from cpu-feature-registers.rst
  arm64: Sort registers in cpu-feature-registers.rst
  arm64: Document missing bitfields in cpu-feature-registers.rst
  arm64: Don't number registers in cpu-feature-registers.rst

12 files changed, 440 insertions, 305 deletions

diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index add66afc7b03..f603afe323d6 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,240 +113,375 @@ infrastructure:
 4. List of registers with visible features
 -------------------------------------------
 
-  1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | RNDR                         | [63-60] |    y    |
-     +------------------------------+---------+---------+
-     | TS                           | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | FHM                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | DP                           | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SM4                          | [43-40] |    y    |
-     +------------------------------+---------+---------+
-     | SM3                          | [39-36] |    y    |
-     +------------------------------+---------+---------+
-     | SHA3                         | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | RDM                          | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | ATOMICS                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | CRC32                        | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SHA2                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SHA1                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-
-
-  2) ID_AA64PFR0_EL1 - Processor Feature Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | DIT                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | MPAM                         | [43-40] |    n    |
-     +------------------------------+---------+---------+
-     | SVE                          | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | GIC                          | [27-24] |    n    |
-     +------------------------------+---------+---------+
-     | AdvSIMD                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | FP                           | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | EL3                          | [15-12] |    n    |
-     +------------------------------+---------+---------+
-     | EL2                          | [11-8]  |    n    |
-     +------------------------------+---------+---------+
-     | EL1                          | [7-4]   |    n    |
-     +------------------------------+---------+---------+
-     | EL0                          | [3-0]   |    n    |
-     +------------------------------+---------+---------+
-
-
-  3) ID_AA64PFR1_EL1 - Processor Feature Register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | SME                          | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | MTE                          | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | SSBS                         | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | BT                           | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-
-  4) MIDR_EL1 - Main ID Register
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | Implementer                  | [31-24] |    y    |
-     +------------------------------+---------+---------+
-     | Variant                      | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | Architecture                 | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | PartNum                      | [15-4]  |    y    |
-     +------------------------------+---------+---------+
-     | Revision                     | [3-0]   |    y    |
-     +------------------------------+---------+---------+
+  ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | F8CVT                        | [31]    |
+     +------------------------------+---------+
+     | F8FMA                        | [30]    |
+     +------------------------------+---------+
+     | F8DP4                        | [29]    |
+     +------------------------------+---------+
+     | F8DP2                        | [28]    |
+     +------------------------------+---------+
+     | F8MM8                        | [27]    |
+     +------------------------------+---------+
+     | F8MM4                        | [26]    |
+     +------------------------------+---------+
+     | F16MM2                       | [15]    |
+     +------------------------------+---------+
+     | F8E4M3                       | [1]     |
+     +------------------------------+---------+
+     | F8E5M2                       | [0]     |
+     +------------------------------+---------+
+
+  ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | RNDR                         | [63-60] |
+     +------------------------------+---------+
+     | TS                           | [55-52] |
+     +------------------------------+---------+
+     | FHM                          | [51-48] |
+     +------------------------------+---------+
+     | DP                           | [47-44] |
+     +------------------------------+---------+
+     | SM4                          | [43-40] |
+     +------------------------------+---------+
+     | SM3                          | [39-36] |
+     +------------------------------+---------+
+     | SHA3                         | [35-32] |
+     +------------------------------+---------+
+     | RDM                          | [31-28] |
+     +------------------------------+---------+
+     | ATOMICS                      | [23-20] |
+     +------------------------------+---------+
+     | CRC32                        | [19-16] |
+     +------------------------------+---------+
+     | SHA2                         | [15-12] |
+     +------------------------------+---------+
+     | SHA1                         | [11-8]  |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+
+
+  ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | LS64                         | [63-60] |
+     +------------------------------+---------+
+     | I8MM                         | [55-52] |
+     +------------------------------+---------+
+     | DGH                          | [51-48] |
+     +------------------------------+---------+
+     | BF16                         | [47-44] |
+     +------------------------------+---------+
+     | SB                           | [39-36] |
+     +------------------------------+---------+
+     | FRINTTS                      | [35-32] |
+     +------------------------------+---------+
+     | GPI                          | [31-28] |
+     +------------------------------+---------+
+     | GPA                          | [27-24] |
+     +------------------------------+---------+
+     | LRCPC                        | [23-20] |
+     +------------------------------+---------+
+     | FCMA                         | [19-16] |
+     +------------------------------+---------+
+     | JSCVT                        | [15-12] |
+     +------------------------------+---------+
+     | API                          | [11-8]  |
+     +------------------------------+---------+
+     | APA                          | [7-4]   |
+     +------------------------------+---------+
+     | DPB                          | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | LUT                          | [59-56] |
+     +------------------------------+---------+
+     | CSSC                         | [55-52] |
+     +------------------------------+---------+
+     | RPRFM                        | [51-48] |
+     +------------------------------+---------+
+     | BC                           | [23-20] |
+     +------------------------------+---------+
+     | MOPS                         | [19-16] |
+     +------------------------------+---------+
+     | APA3                         | [15-12] |
+     +------------------------------+---------+
+     | GPA3                         | [11-8]  |
+     +------------------------------+---------+
+     | RPRES                        | [7-4]   |
+     +------------------------------+---------+
+     | WFXT                         | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPRCVT                       | [31-28] |
+     +------------------------------+---------+
+     | LSFE                         | [19-16] |
+     +------------------------------+---------+
+     | FAMINMAX                     | [7-4]   |
+     +------------------------------+---------+
+
+  ID_AA64MMFR0_EL1 - Memory model feature register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | ECV                          | [63-60] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR1_EL1 - Memory model feature register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | AFP                          | [47-44] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR2_EL1 - Memory model feature register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | AT                           | [35-32] |
+     +------------------------------+---------+
+
+  ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | S1POE                        | [19-16] |
+     +------------------------------+---------+
+
+  ID_AA64PFR0_EL1 - Processor Feature Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | DIT                          | [51-48] |
+     +------------------------------+---------+
+     | SVE                          | [35-32] |
+     +------------------------------+---------+
+     | AdvSIMD                      | [23-20] |
+     +------------------------------+---------+
+     | FP                           | [19-16] |
+     +------------------------------+---------+
+
+
+  ID_AA64PFR1_EL1 - Processor Feature Register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | GCS                          | [47-44] |
+     +------------------------------+---------+
+     | SME                          | [27-24] |
+     +------------------------------+---------+
+     | MTE                          | [11-8]  |
+     +------------------------------+---------+
+     | SSBS                         | [7-4]   |
+     +------------------------------+---------+
+     | BT                           | [3-0]   |
+     +------------------------------+---------+
+
+  ID_AA64PFR2_EL1 - Processor Feature Register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPMR                         | [35-32] |
+     +------------------------------+---------+
+     | MTEFAR                       | [11-8]  |
+     +------------------------------+---------+
+     | MTESTOREONLY                 | [7-4]   |
+     +------------------------------+---------+
+
+  ID_AA64SMFR0_EL1 - SME feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FA64                         | [63]    |
+     +------------------------------+---------+
+     | LUT6                         | [61]    |
+     +------------------------------+---------+
+     | LUTv2                        | [60]    |
+     +------------------------------+---------+
+     | SMEver                       | [59-56] |
+     +------------------------------+---------+
+     | I16I64                       | [55-52] |
+     +------------------------------+---------+
+     | F64F64                       | [48]    |
+     +------------------------------+---------+
+     | I16I32                       | [47-44] |
+     +------------------------------+---------+
+     | B16B16                       | [43]    |
+     +------------------------------+---------+
+     | F16F16                       | [42]    |
+     +------------------------------+---------+
+     | F8F16                        | [41]    |
+     +------------------------------+---------+
+     | F8F32                        | [40]    |
+     +------------------------------+---------+
+     | I8I32                        | [39-36] |
+     +------------------------------+---------+
+     | F16F32                       | [35]    |
+     +------------------------------+---------+
+     | B16F32                       | [34]    |
+     +------------------------------+---------+
+     | BI32I32                      | [33]    |
+     +------------------------------+---------+
+     | F32F32                       | [32]    |
+     +------------------------------+---------+
+     | SF8FMA                       | [30]    |
+     +------------------------------+---------+
+     | SF8DP4                       | [29]    |
+     +------------------------------+---------+
+     | SF8DP2                       | [28]    |
+     +------------------------------+---------+
+     | SBitPerm                     | [25]    |
+     +------------------------------+---------+
+     | AES                          | [24]    |
+     +------------------------------+---------+
+     | SFEXPA                       | [23]    |
+     +------------------------------+---------+
+     | STMOP                        | [16]    |
+     +------------------------------+---------+
+     | SMOP4                        | [0]     |
+     +------------------------------+---------+
+
+  ID_AA64ZFR0_EL1 - SVE feature ID register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | F64MM                        | [59-56] |
+     +------------------------------+---------+
+     | F32MM                        | [55-52] |
+     +------------------------------+---------+
+     | F16MM                        | [51-48] |
+     +------------------------------+---------+
+     | I8MM                         | [47-44] |
+     +------------------------------+---------+
+     | SM4                          | [43-40] |
+     +------------------------------+---------+
+     | SHA3                         | [35-32] |
+     +------------------------------+---------+
+     | B16B16                       | [27-24] |
+     +------------------------------+---------+
+     | BF16                         | [23-20] |
+     +------------------------------+---------+
+     | BitPerm                      | [19-16] |
+     +------------------------------+---------+
+     | EltPerm                      | [15-12] |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+     | SVEVer                       | [3-0]   |
+     +------------------------------+---------+
+
+  ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | CRC32                        | [19-16] |
+     +------------------------------+---------+
+     | SHA2                         | [15-12] |
+     +------------------------------+---------+
+     | SHA1                         | [11-8]  |
+     +------------------------------+---------+
+     | AES                          | [7-4]   |
+     +------------------------------+---------+
+
+  ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | I8MM                         | [27-24] |
+     +------------------------------+---------+
+     | BF16                         | [23-20] |
+     +------------------------------+---------+
+     | SB                           | [15-12] |
+     +------------------------------+---------+
+     | FHM                          | [11-8]  |
+     +------------------------------+---------+
+     | DP                           | [7-4]   |
+     +------------------------------+---------+
+
+  ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | SSBS                         | [7-4]   |
+     +------------------------------+---------+
+
+  MIDR_EL1 - Main ID Register
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | Implementer                  | [31-24] |
+     +------------------------------+---------+
+     | Variant                      | [23-20] |
+     +------------------------------+---------+
+     | Architecture                 | [19-16] |
+     +------------------------------+---------+
+     | PartNum                      | [15-4]  |
+     +------------------------------+---------+
+     | Revision                     | [3-0]   |
+     +------------------------------+---------+
 
    NOTE: The 'visible' fields of MIDR_EL1 will contain the value
    as available on the CPU where it is fetched and is not a system
    wide safe value.
 
-  5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | I8MM                         | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | DGH                          | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | BF16                         | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SB                           | [39-36] |    y    |
-     +------------------------------+---------+---------+
-     | FRINTTS                      | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | GPI                          | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | GPA                          | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | LRCPC                        | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | FCMA                         | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | JSCVT                        | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | API                          | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | APA                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | DPB                          | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  6) ID_AA64MMFR0_EL1 - Memory model feature register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | ECV                          | [63-60] |    y    |
-     +------------------------------+---------+---------+
-
-  7) ID_AA64MMFR2_EL1 - Memory model feature register 2
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | AT                           | [35-32] |    y    |
-     +------------------------------+---------+---------+
-
-  8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | F64MM                        | [59-56] |    y    |
-     +------------------------------+---------+---------+
-     | F32MM                        | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | I8MM                         | [47-44] |    y    |
-     +------------------------------+---------+---------+
-     | SM4                          | [43-40] |    y    |
-     +------------------------------+---------+---------+
-     | SHA3                         | [35-32] |    y    |
-     +------------------------------+---------+---------+
-     | B16B16                       | [27-24] |    y    |
-     +------------------------------+---------+---------+
-     | BF16                         | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | BitPerm                      | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | SVEVer                       | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  8) ID_AA64MMFR1_EL1 - Memory model feature register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | AFP                          | [47-44] |    y    |
-     +------------------------------+---------+---------+
-
-  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | CSSC                         | [55-52] |    y    |
-     +------------------------------+---------+---------+
-     | RPRFM                        | [51-48] |    y    |
-     +------------------------------+---------+---------+
-     | BC                           | [23-20] |    y    |
-     +------------------------------+---------+---------+
-     | MOPS                         | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | APA3                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | GPA3                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | RPRES                        | [7-4]   |    y    |
-     +------------------------------+---------+---------+
-     | WFXT                         | [3-0]   |    y    |
-     +------------------------------+---------+---------+
-
-  10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | FPDP                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-
-  11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | SIMDFMAC                     | [31-28] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDSP                       | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDInt                      | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SIMDLS                       | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-
-  12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
-
-     +------------------------------+---------+---------+
-     | Name                         |  bits   | visible |
-     +------------------------------+---------+---------+
-     | CRC32                        | [19-16] |    y    |
-     +------------------------------+---------+---------+
-     | SHA2                         | [15-12] |    y    |
-     +------------------------------+---------+---------+
-     | SHA1                         | [11-8]  |    y    |
-     +------------------------------+---------+---------+
-     | AES                          | [7-4]   |    y    |
-     +------------------------------+---------+---------+
+  MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | FPDP                         | [11-8]  |
+     +------------------------------+---------+
+
+  MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+
+     +------------------------------+---------+
+     | Name                         |  bits   |
+     +------------------------------+---------+
+     | SIMDFMAC                     | [31-28] |
+     +------------------------------+---------+
+     | FPHP                         | [27-24] |
+     +------------------------------+---------+
+     | SIMDHP                       | [23-20] |
+     +------------------------------+---------+
+     | SIMDSP                       | [19-16] |
+     +------------------------------+---------+
+     | SIMDInt                      | [15-12] |
+     +------------------------------+---------+
+     | SIMDLS                       | [11-8]  |
+     +------------------------------+---------+
 
 
 Appendix I: Example
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 014aa1c215a1..57c778446936 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -242,10 +242,14 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3AE   | #4193784        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | C1-Premium      | #3683289        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Premium      | #4193780        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Pro          | #4193714        | ARM64_ERRATUM_4193714       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | C1-Ultra        | #3683289        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | C1-Ultra        | #4193780        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-500         | #562869,        | ARM_SMMU_MMU_500_CPRE_ERRATA|
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b3afe0688919..fc57d90d92c1 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2116,6 +2116,8 @@ config ARM64_BTI_KERNEL
 	depends on !CC_IS_GCC || GCC_VERSION >= 100100
 	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
 	depends on !CC_IS_GCC
+	# https://github.com/llvm/llvm-project/issues/215547
+	depends on !CC_IS_CLANG || CLANG_VERSION < 210000
 	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
 	help
 	  Build the kernel with Branch Target Identification annotations
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index a57870fa96db..d90040fb9de6 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -878,11 +878,11 @@ static inline bool system_supports_pmuv3(void)
 	return cpus_have_final_cap(ARM64_HAS_PMUV3);
 }
 
-bool cpu_supports_bbml2_noabort(void);
+bool cpu_supports_bbml3(void);
 
-static inline bool system_supports_bbml2_noabort(void)
+static inline bool system_supports_bbml3(void)
 {
-	return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOABORT);
+	return alternative_has_cap_unlikely(ARM64_HAS_BBML3);
 }
 
 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 1b9f0cda1336..1fa29616e586 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -82,6 +82,7 @@
 #define ARM_CPU_PART_CORTEX_X1		0xD44
 #define ARM_CPU_PART_CORTEX_A510	0xD46
 #define ARM_CPU_PART_CORTEX_A520	0xD80
+#define ARM_CPU_PART_CORTEX_A520AE	0xD88
 #define ARM_CPU_PART_CORTEX_A710	0xD47
 #define ARM_CPU_PART_CORTEX_A715	0xD4D
 #define ARM_CPU_PART_CORTEX_X2		0xD48
@@ -99,6 +100,7 @@
 #define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_C1_ULTRA		0xD8C
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
+#define ARM_CPU_PART_C1_NANO		0xD8A
 #define ARM_CPU_PART_C1_PRO		0xD8B
 #define ARM_CPU_PART_C1_PREMIUM		0xD90
 
@@ -176,6 +178,7 @@
 #define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
+#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE)
 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
@@ -193,6 +196,7 @@
 #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
+#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
 #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
 #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9a22df0c5120..4025d51d2d93 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2131,45 +2131,39 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
 	return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
 }
 
-bool cpu_supports_bbml2_noabort(void)
+bool cpu_supports_bbml3(void)
 {
-	/*
-	 * We want to allow usage of BBML2 in as wide a range of kernel contexts
-	 * as possible. This list is therefore an allow-list of known-good
-	 * implementations that both support BBML2 and additionally, fulfill the
-	 * extra constraint of never generating TLB conflict aborts when using
-	 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain
-	 * kernel contexts difficult to prove safe against recursive aborts).
-	 *
-	 * Note that implementations can only be considered "known-good" if their
-	 * implementors attest to the fact that the implementation never raises
-	 * TLB conflict aborts for BBML2 mapping granularity changes.
-	 */
-	static const struct midr_range supports_bbml2_noabort_list[] = {
+	/* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */
+	static const struct midr_range supports_bbml3_list[] = {
 		MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
 		MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
 		MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf),
 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
 		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
+		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
+		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
+		MIDR_ALL_VERSIONS(MIDR_C1_PRO),
+		/* Erratum 3683289 fixed in r1p1 */
+		MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf),
+		MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf),
 		{}
 	};
+	u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1);
 
-	/* Does our cpu guarantee to never raise TLB conflict aborts? */
-	if (!is_midr_in_range_list(supports_bbml2_noabort_list))
-		return false;
-
-	/*
-	 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care
-	 * about whether the MIDR check passes.
-	 */
+	if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3)
+		return true;
 
-	return true;
+	return is_midr_in_range_list(supports_bbml3_list);
 }
 
-static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope)
+static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope)
 {
-	return cpu_supports_bbml2_noabort();
+	return cpu_supports_bbml3();
 }
 
 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
@@ -3062,10 +3056,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
 	},
 	{
-		.desc = "BBM Level 2 without TLB conflict abort",
-		.capability = ARM64_HAS_BBML2_NOABORT,
+		.desc = "BBM Level 3",
+		.capability = ARM64_HAS_BBML3,
 		.type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE,
-		.matches = has_bbml2_noabort,
+		.matches = has_bbml3,
 	},
 	{
 		.desc = "52-bit Virtual Addressing for KVM (LPA2)",
diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c
index 2de12656b4d8..0acab179fc1a 100644
--- a/arch/arm64/mm/contpte.c
+++ b/arch/arm64/mm/contpte.c
@@ -89,7 +89,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr,
 	}
 
 	/*
-	 * On eliding the __tlb_flush_range() under BBML2+noabort:
+	 * On eliding the __tlb_flush_range() under BBML3:
 	 *
 	 * NOTE: Instead of using N=16 as the contiguous block length, we use
 	 *       N=4 for clarity.
@@ -135,7 +135,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr,
 	 * contiguous TLB entry, which is a micro-optimisation opportunity,
 	 * but does not affect correctness.
 	 *
-	 * In the BBML2 case, the change is avoiding the intermediate tlbi+dsb.
+	 * In the BBML3 case, the change is avoiding the intermediate tlbi+dsb.
 	 * This means a few things, but notably other PEs will still "see" any
 	 * stale cached TLB entries. This could lead to a "contiguous bit
 	 * misprogramming" issue until the final tlbi+dsb of the changed page,
@@ -158,21 +158,16 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr,
 	 *  are present, and a write is made to this address, do we fault or
 	 *  is the write permitted (via amalgamation)?
 	 *
-	 * The relevant Arm ARM DDI 0487L.a requirements are RNGLXZ and RJQQTC,
-	 * and together state that when BBML1 or BBML2 are implemented, either
-	 * a TLB conflict abort is raised (which we expressly forbid), or will
-	 * "produce an OA, access permissions, and memory attributes that are
-	 * consistent with any of the programmed translation table values".
-	 *
-	 * That is to say, will either raise a TLB conflict, or produce one of
-	 * the cached TLB entries, but never amalgamate.
+	 * With BBML3 implemented, no TLB conflict abort is raised and the OA,
+	 * access permissions and memory attributes produced is one of the cached
+	 * TLB entries, but never amalgamate.
 	 *
 	 * Thus, as the page tables are only considered "consistent" after
 	 * the final tlbi+dsb (which evicts both the single stale (RW,n) TLB
 	 * entry as well as the new contiguous (RO,c) TLB entry), omitting the
 	 * initial tlbi+dsb is correct.
 	 *
-	 * It is also important to note that at the end of the BBML2 folding
+	 * It is also important to note that at the end of the BBML3 folding
 	 * case, we are still left with potentially all N TLB entries still
 	 * cached (the N-1 non-contiguous ptes, and the single contiguous
 	 * block). However, over time, natural TLB pressure will cause the
@@ -214,7 +209,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr,
 	 *
 	 *                  |____| <--- tlbi + dsb
 	 *
-	 * For BBML2, we again remove the intermediate tlbi+dsb. Here, there
+	 * For BBML3, we again remove the intermediate tlbi+dsb. Here, there
 	 * are no issues, as the final tlbi+dsb covering the changed page is
 	 * guaranteed to remove the original large contiguous (RW,c) TLB entry,
 	 * as well as the intermediate (RW,n) TLB entry; the next access will
@@ -224,7 +219,7 @@ static void contpte_convert(struct mm_struct *mm, unsigned long addr,
 	 * regardless.
 	 */
 
-	if (!system_supports_bbml2_noabort())
+	if (!system_supports_bbml3())
 		__flush_tlb_range(&vma, start_addr, addr, PAGE_SIZE, 3,
 				  TLBF_NOWALKCACHE);
 
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index a25d8beacc83..fad71d6bff40 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -779,18 +779,18 @@ out:
 
 static inline bool force_pte_mapping(void)
 {
-	const bool bbml2 = system_capabilities_finalized() ?
-		system_supports_bbml2_noabort() : cpu_supports_bbml2_noabort();
+	const bool bbml3 = system_capabilities_finalized() ?
+		system_supports_bbml3() : cpu_supports_bbml3();
 
 	if (debug_pagealloc_enabled())
 		return true;
-	if (bbml2)
+	if (bbml3)
 		return false;
 	return rodata_full || arm64_kfence_can_set_direct_map() || is_realm_world();
 }
 
 static DEFINE_MUTEX(pgtable_split_lock);
-static bool linear_map_requires_bbml2;
+static bool linear_map_requires_bbml3;
 
 int split_kernel_leaf_mapping(unsigned long start, unsigned long end)
 {
@@ -803,15 +803,15 @@ int split_kernel_leaf_mapping(unsigned long start, unsigned long end)
 	 * always pte-mapped), we must not go any further because taking the
 	 * mutex below may sleep. Do not call force_pte_mapping() here because
 	 * it could return a confusing result if called from a secondary cpu
-	 * prior to finalizing caps. Instead, linear_map_requires_bbml2 gives us
+	 * prior to finalizing caps. Instead, linear_map_requires_bbml3 gives us
 	 * what we need.
 	 */
-	if (!linear_map_requires_bbml2 || is_kfence_address((void *)start))
+	if (!linear_map_requires_bbml3 || is_kfence_address((void *)start))
 		return 0;
 
-	if (!system_supports_bbml2_noabort()) {
+	if (!system_supports_bbml3()) {
 		/*
-		 * !BBML2_NOABORT systems should not be trying to change
+		 * BBML3 systems should not be trying to change
 		 * permissions on anything that is not pte-mapped in the first
 		 * place. Just return early and let the permission change code
 		 * raise a warning if not already pte-mapped.
@@ -828,8 +828,8 @@ int split_kernel_leaf_mapping(unsigned long start, unsigned long end)
 
 		/*
 		 * Boot-time: Started secondary cpus but don't know if they
-		 * support BBML2_NOABORT yet. Can't allow splitting in this
-		 * window in case they don't.
+		 * support BBML3 yet. Can't allow splitting in this window
+		 * in case they don't.
 		 */
 		if (WARN_ON(num_online_cpus() > 1))
 			return -EBUSY;
@@ -934,11 +934,11 @@ static int range_split_to_ptes(unsigned long start, unsigned long end, gfp_t gfp
 	return ret;
 }
 
-u32 idmap_kpti_bbml2_flag;
+u32 idmap_kpti_bbml3_flag;
 
-static void __init init_idmap_kpti_bbml2_flag(void)
+static void __init init_idmap_kpti_bbml3_flag(void)
 {
-	WRITE_ONCE(idmap_kpti_bbml2_flag, 1);
+	WRITE_ONCE(idmap_kpti_bbml3_flag, 1);
 	/* Must be visible to other CPUs before stop_machine() is called. */
 	smp_mb();
 }
@@ -947,7 +947,7 @@ static int __init linear_map_split_to_ptes(void *__unused)
 {
 	/*
 	 * Repainting the linear map must be done by CPU0 (the boot CPU) because
-	 * that's the only CPU that we know supports BBML2. The other CPUs will
+	 * that's the only CPU that we know supports BBML3. The other CPUs will
 	 * be held in a waiting area with the idmap active.
 	 */
 	if (!smp_processor_id()) {
@@ -960,7 +960,7 @@ static int __init linear_map_split_to_ptes(void *__unused)
 		/*
 		 * Wait for all secondary CPUs to be put into the waiting area.
 		 */
-		smp_cond_load_acquire(&idmap_kpti_bbml2_flag, VAL == num_online_cpus());
+		smp_cond_load_acquire(&idmap_kpti_bbml3_flag, VAL == num_online_cpus());
 
 		/*
 		 * Walk all of the linear map [lstart, lend), except the kernel
@@ -979,7 +979,7 @@ static int __init linear_map_split_to_ptes(void *__unused)
 		 * Relies on dsb in flush_tlb_kernel_range() to avoid reordering
 		 * before any page table split operations.
 		 */
-		WRITE_ONCE(idmap_kpti_bbml2_flag, 0);
+		WRITE_ONCE(idmap_kpti_bbml3_flag, 0);
 	} else {
 		typedef void (wait_split_fn)(void);
 		extern wait_split_fn wait_linear_map_split_to_ptes;
@@ -988,7 +988,7 @@ static int __init linear_map_split_to_ptes(void *__unused)
 		wait_fn = (void *)__pa_symbol(wait_linear_map_split_to_ptes);
 
 		/*
-		 * At least one secondary CPU doesn't support BBML2 so cannot
+		 * At least one secondary CPU doesn't support BBML3 so cannot
 		 * tolerate the size of the live mappings changing. So have the
 		 * secondary CPUs wait for the boot CPU to make the changes
 		 * with the idmap active and init_mm inactive.
@@ -1003,8 +1003,8 @@ static int __init linear_map_split_to_ptes(void *__unused)
 
 void __init linear_map_maybe_split_to_ptes(void)
 {
-	if (linear_map_requires_bbml2 && !system_supports_bbml2_noabort()) {
-		init_idmap_kpti_bbml2_flag();
+	if (linear_map_requires_bbml3 && !system_supports_bbml3()) {
+		init_idmap_kpti_bbml3_flag();
 		stop_machine(linear_map_split_to_ptes, NULL, cpu_online_mask);
 	}
 }
@@ -1127,7 +1127,7 @@ bool arch_kfence_init_pool(void)
 	mutex_unlock(&pgtable_split_lock);
 
 	/*
-	 * Since the system supports bbml2_noabort, tlb invalidation is not
+	 * Since the system supports bbml3, tlb invalidation is not
 	 * required here; the pgtable mappings have been split to pte but larger
 	 * entries may safely linger in the TLB.
 	 */
@@ -1166,7 +1166,7 @@ static void __init map_mem(void)
 
 	arm64_kfence_map_pool();
 
-	linear_map_requires_bbml2 = !force_pte_mapping() && can_set_direct_map();
+	linear_map_requires_bbml3 = !force_pte_mapping() && can_set_direct_map();
 
 	if (force_pte_mapping())
 		flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS;
@@ -1333,7 +1333,7 @@ void __init kpti_install_ng_mappings(void)
 	if (arm64_use_ng_mappings)
 		return;
 
-	init_idmap_kpti_bbml2_flag();
+	init_idmap_kpti_bbml3_flag();
 	stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask);
 }
 
@@ -1394,7 +1394,7 @@ void __pi_map_range(phys_addr_t *pte, u64 start, u64 end, phys_addr_t pa,
 		    u64 va_offset);
 
 static u8 idmap_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init,
-	  kpti_bbml2_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init;
+	  kpti_bbml3_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_after_init;
 
 static void __init create_idmap(void)
 {
@@ -1406,17 +1406,17 @@ static void __init create_idmap(void)
 		       IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false,
 		       __phys_to_virt(ptep) - ptep);
 
-	if (linear_map_requires_bbml2 ||
+	if (linear_map_requires_bbml3 ||
 	    (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && !arm64_use_ng_mappings)) {
-		phys_addr_t pa = __pa_symbol(&idmap_kpti_bbml2_flag);
+		phys_addr_t pa = __pa_symbol(&idmap_kpti_bbml3_flag);
 
 		/*
 		 * The KPTI G-to-nG conversion code needs a read-write mapping
 		 * of its synchronization flag in the ID map. This is also used
 		 * when splitting the linear map to ptes if a secondary CPU
-		 * doesn't support bbml2.
+		 * doesn't support bbml3.
 		 */
-		ptep = __pa_symbol(kpti_bbml2_ptes);
+		ptep = __pa_symbol(kpti_bbml3_ptes);
 		__pi_map_range(&ptep, pa, pa + sizeof(u32), pa, PAGE_KERNEL,
 			       IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false,
 			       __phys_to_virt(ptep) - ptep);
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 22866b49be37..f4e4e71a0ea8 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -287,7 +287,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings)
 
 	mov	x5, x3				// preserve temp_pte arg
 	mrs	swapper_ttb, ttbr1_el1
-	adr_l	flag_ptr, idmap_kpti_bbml2_flag
+	adr_l	flag_ptr, idmap_kpti_bbml3_flag
 
 	cbnz	cpu, __idmap_kpti_secondary
 
@@ -445,7 +445,7 @@ SYM_TYPED_FUNC_START(wait_linear_map_split_to_ptes)
 	flag_ptr	.req	x4
 
 	mrs     swapper_ttb, ttbr1_el1
-	adr_l   flag_ptr, idmap_kpti_bbml2_flag
+	adr_l   flag_ptr, idmap_kpti_bbml3_flag
 	__idmap_cpu_set_reserved_ttbr1 x16, x17
 
 scondary_cpu_wait:
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 9b85a84f6fd4..0b94837ac238 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 #
-# Internal CPU capabilities constants, keep this list sorted
+# Internal CPU capabilities constants
 
 ALWAYS_BOOT
 ALWAYS_SYSTEM
@@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5
 HAS_ADDRESS_AUTH_IMP_DEF
 HAS_AMU_EXTN
 HAS_ARMv8_4_TTL
+HAS_BBML3
 HAS_CACHE_DIC
 HAS_CACHE_IDC
 HAS_CNP
@@ -51,7 +52,6 @@ HAS_LS64_V
 HAS_LSUI
 HAS_MOPS
 HAS_NESTED_VIRT
-HAS_BBML2_NOABORT
 HAS_PAN
 HAS_PMUV3
 HAS_S1PIE
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7cb61aca3797..e070ada06196 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2259,6 +2259,7 @@ UnsignedEnum	55:52	BBM
 	0b0000	0
 	0b0001	1
 	0b0010	2
+	0b0011	3
 EndEnum
 UnsignedEnum	51:48	TTL
 	0b0000	NI
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index 1ed8a6f29dc4..01492fb52659 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -208,7 +208,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
 		feat_mask |= ARM_SMMU_FEAT_VAX;
 	}
 
-	if (system_supports_bbml2_noabort())
+	if (system_supports_bbml3())
 		feat_mask |= ARM_SMMU_FEAT_BBML2;
 
 	if ((smmu->features & feat_mask) != feat_mask)