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authorOvidiu Bunea <ovidiu.bunea@amd.com>2026-08-04 16:04:18 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-08-25 18:25:27 -0400
commit3b381dc0ed89eb04c2b4ad2ed006fc15ee802d7f (patch)
tree73996999344310f9e17272903e0c6079dad784a2 /drivers/gpu
parent0dd25075be610e5a597fafa276a775ec4ebe6098 (diff)
downloadlinux-next-3b381dc0ed89eb04c2b4ad2ed006fc15ee802d7f.tar.gz
linux-next-3b381dc0ed89eb04c2b4ad2ed006fc15ee802d7f.zip
drm/amd/display: Add DC_BLS command
[why & how] In the future, DC will off-load block-level initialization to DMUB. In preparation, update dmub_cmd.h with the command for better tracking. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f0231f355fa7..c273d97ec88d 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1170,6 +1170,16 @@ enum dmub_ips_comand_type {
};
/**
+ * enum dmub_dc_bls_command_type - DC_BLS subcommands.
+ */
+enum dmub_dc_bls_command_type {
+ /**
+ * Placeholder for block-level initialization of the DCHVM
+ */
+ DMUB_CMD__DC_BLS_DCHVM_INIT = 0,
+};
+
+/**
* enum dmub_cursor_offload_comand_type - Cursor offload subcommands.
*/
enum dmub_cursor_offload_comand_type {
@@ -2009,6 +2019,11 @@ enum dmub_cmd_type {
DMUB_CMD__PANEL_POLARITY = 97,
/**
+ * Command type used for all DC_BLS commands.
+ */
+ DMUB_CMD__DC_BLS = 98,
+
+ /**
* Command type use for VBIOS shared commands.
*/
DMUB_CMD__VBIOS = 128,
@@ -2941,6 +2956,25 @@ struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
};
/**
+ * Data passed from driver to FW in a DMUB_CMD__DC_BLS_DCHVM_INIT command.
+ */
+struct dmub_cmd_dc_bls_dchvm_init_data {
+ /**
+ * The value to program to rIOMMU PCTRL register. x86 cannot access this SMN
+ * register, so the write is performed by DMCUB on the driver's behalf.
+ */
+ uint32_t riommu_pctrl_val; /* r */
+};
+
+/**
+ * Definition of a DMUB_CMD__DC_BLS_DCHVM_INIT command.
+ */
+struct dmub_rb_cmd_dc_bls_dchvm_init {
+ struct dmub_cmd_header header;
+ struct dmub_cmd_dc_bls_dchvm_init_data data;
+};
+
+/**
* enum dmub_idle_opt_dc_power_state - DC power states.
*/
enum dmub_idle_opt_dc_power_state {
@@ -7988,6 +8022,8 @@ union dmub_rb_cmd {
struct dmub_rb_cmd_panel_polarity_enable panel_polarity_enable;
struct dmub_rb_cmd_panel_polarity_get_bias panel_polarity_get_bias;
struct dmub_rb_cmd_panel_polarity_reset panel_polarity_reset;
+
+ struct dmub_rb_cmd_dc_bls_dchvm_init dc_bls_dchvm_init;
};
/**