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authorVinod Govindapillai <vinod.govindapillai@intel.com>2026-06-15 23:33:51 +0300
committerVinod Govindapillai <vinod.govindapillai@intel.com>2026-07-15 11:28:30 +0300
commit490de57216725dc9ae3de85d46dfd4eb73dbd233 (patch)
treeafa496a0ebe406ead022edafbac6e5817c2bae7f /drivers
parentfb8a24c0799d9b1a544c26b5fba4f559e127cfcd (diff)
downloadlinux-next-490de57216725dc9ae3de85d46dfd4eb73dbd233.tar.gz
linux-next-490de57216725dc9ae3de85d46dfd4eb73dbd233.zip
drm/i915/display: sagv pre/post plane calls to check pmdemand support
For pmdemand cases, no need to even calculate the masks based on the qgv points index. Though the current logic avoids setting the registers based on the pmdemand support, some qgv point masks are compared in vain and do nothing. So leave early if pmdemand is supported. Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260615203355.218578-4-vinod.govindapillai@intel.com
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/display/skl_watermark.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a4ce21d4c024..ec1bfe46edef 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -275,6 +275,9 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!intel_has_sagv(display))
return;
+ if (HAS_PMDEMAND(display))
+ return;
+
if (DISPLAY_VER(display) >= 11)
icl_sagv_pre_plane_update(state);
else
@@ -295,6 +298,9 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!intel_has_sagv(display))
return;
+ if (HAS_PMDEMAND(display))
+ return;
+
if (DISPLAY_VER(display) >= 11)
icl_sagv_post_plane_update(state);
else