diff options
| author | Heiko Stuebner <heiko.stuebner@cherry.de> | 2026-03-04 13:14:26 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-07-07 11:39:41 +0200 |
| commit | 778dd30867ad783b6903b0aa24a0ab5e97c2dff6 (patch) | |
| tree | 9c0787137fc2ee5e44cc40c9c59fcd712fa1bc30 /drivers | |
| parent | 13b10571cc353448275365ede1a5396d20dfe839 (diff) | |
| download | linux-next-778dd30867ad783b6903b0aa24a0ab5e97c2dff6.tar.gz linux-next-778dd30867ad783b6903b0aa24a0ab5e97c2dff6.zip | |
clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs
Right now dclk_vop2_src is not allowed to change its parent, while
the other two dclks are allowed to do this.
All three VPs can drive non-static outputs (HDMI, DP, eDP) and even the
eDP can also support full DP connections (though no DP+).
Therefore remove the CLK_SET_RATE_NO_REPARENT flag, to allow VP2 the same
flexibility in acquiring its clock rate.
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schuz@cherry.de>
Tested-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://patch.msgid.link/20260304121426.1184680-3-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3588.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index ff95f6c28b89..f20764b0ffcf 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -2102,7 +2102,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(52), 11, GFLAGS), - COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, 0, RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 12, GFLAGS), COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, |