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authorJie Zhang <jie.zhang@oss.qualcomm.com>2026-06-05 01:38:19 +0530
committerRob Clark <robin.clark@oss.qualcomm.com>2026-07-16 13:37:22 -0700
commitfc7ccbc6174b79ffab5be5dca5b6e253df22f030 (patch)
treea4bb653365fc0b80446a2225474ffd5aa5ee7775 /drivers
parentb303e1d52811de7d1bcf793560754d4df68d4a1c (diff)
downloadlinux-next-fc7ccbc6174b79ffab5be5dca5b6e253df22f030.tar.gz
linux-next-fc7ccbc6174b79ffab5be5dca5b6e253df22f030.zip
drm/msm/a6xx: Fix A663 GPUCC register list for state capture
The GPUCC register list for A663 is incorrect, which can cause out-of-bounds register access during GPU state capture. Update it to use the correct register ranges. Fixes: 5773cce8615c ("drm/msm/a6xx: Add support for A663") Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/730656/ Message-ID: <20260605-assorted-fixes-june-v1-3-2caa04f7287c@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 166365359fa6..2a62a22077f9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -1244,7 +1244,9 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
&a6xx_state->gmu_registers[1], true);
- if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu))
+ if (adreno_is_a621(adreno_gpu) ||
+ adreno_is_a623(adreno_gpu) ||
+ adreno_is_a663(adreno_gpu))
_a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg,
&a6xx_state->gmu_registers[2], false);
else