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| author | Rounak Das <rounakdas2025@gmail.com> | 2026-07-08 13:11:35 +0400 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2026-07-10 18:49:17 -0700 |
| commit | 11f5fd36076a2ef229ec5062c06954c955d90f9d (patch) | |
| tree | 9831ebcd30877a6a19757c414d63dc004a109eef /scripts/objdiff | |
| parent | d4486fc3098e176cb4a29fee037216484761f9ca (diff) | |
| download | linux-next-11f5fd36076a2ef229ec5062c06954c955d90f9d.tar.gz linux-next-11f5fd36076a2ef229ec5062c06954c955d90f9d.zip | |
EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error path
Replace the remaining two CONFIG_64BIT ifdefs with the is_s10 flag, so driver
behavior is fully determined by the ECC manager's compatible string rather
than the build architecture.
These two ifdefs guard the double-bit-error path, where SError handling and
the arm_smccc_smc() reboot call are arm64-specific. Switching to is_s10 means
s10_edac_dberr_handler() now compiles on 32-bit as well — this is safe because
all the symbols it depends on (arm_smccc_smc, INTEL_SIP_SMC_ECC_DBE, and the
S10 sysmgr defines) are already available on 32-bit socfpga. Since the
function only executes when is_s10 is true, Arria10 behavior is unaffected.
This is handled separately from the IRQ-index selection change, as the
double-bit-error path is a distinct concern.
Signed-off-by: Rounak Das <rounakdas2025@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Assisted-by: Claude:claude-sonnet-5
Link: https://patch.msgid.link/20260708091135.94114-3-rounakdas2025@gmail.com
Diffstat (limited to 'scripts/objdiff')
0 files changed, 0 insertions, 0 deletions
