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-rw-r--r--sound/soc/mediatek/mt8186/mt8186-afe-clk.c95
-rw-r--r--sound/soc/mediatek/mt8186/mt8186-afe-gpio.c6
-rw-r--r--sound/soc/mediatek/mt8186/mt8186-afe-pcm.c21
3 files changed, 78 insertions, 44 deletions
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-clk.c b/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
index daaca36a2d08..62b008b7caca 100644
--- a/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
@@ -98,7 +98,7 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
- return ret;
+ goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_TOP_APLL1_CK]);
@@ -106,7 +106,7 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_TOP_APLL1_CK], ret);
- return ret;
+ goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
}
/* 180.6336 / 8 = 22.5792MHz */
@@ -114,7 +114,7 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
- return ret;
+ goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_TOP_APLL1_D8]);
@@ -122,7 +122,7 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_TOP_APLL1_D8], ret);
- return ret;
+ goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
@@ -131,7 +131,6 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_CLK26M], ret);
- return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
@@ -141,12 +140,23 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_CLK26M], ret);
- return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
}
return 0;
+
+ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
+ clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
+ afe_priv->clk[CLK_CLK26M]);
+ clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
+ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
+ERR_SELECT_CLK_TOP_MUX_AUD_1:
+ clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[CLK_CLK26M]);
+ clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
+ERR_ENABLE_CLK_TOP_MUX_AUD_1:
+ return ret;
}
static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
@@ -159,7 +169,7 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
- return ret;
+ goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_TOP_APLL2_CK]);
@@ -167,7 +177,7 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_TOP_APLL2_CK], ret);
- return ret;
+ goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
}
/* 196.608 / 8 = 24.576MHz */
@@ -175,7 +185,7 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
- return ret;
+ goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_TOP_APLL2_D8]);
@@ -183,7 +193,7 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_TOP_APLL2_D8], ret);
- return ret;
+ goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
@@ -192,7 +202,6 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_CLK26M], ret);
- return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
@@ -202,12 +211,23 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_CLK26M], ret);
- return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
}
return 0;
+
+ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
+ clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
+ afe_priv->clk[CLK_CLK26M]);
+ clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
+ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
+ERR_SELECT_CLK_TOP_MUX_AUD_2:
+ clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[CLK_CLK26M]);
+ clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
+ERR_ENABLE_CLK_TOP_MUX_AUD_2:
+ return ret;
}
int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)
@@ -268,7 +288,7 @@ int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO],
aud_clks[CLK_CLK26M], ret);
- goto clk_mux_audio_err;
+ goto clk_mux_audio_intbus_err;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
@@ -295,24 +315,22 @@ int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_AFE], ret);
- goto clk_afe_err;
+ goto clk_mux_audio_h_parent_err;
}
return 0;
-clk_afe_err:
- clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
clk_mux_audio_h_parent_err:
-clk_mux_audio_intbus_parent_err:
mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
-clk_mux_audio_intbus_err:
+clk_mux_audio_intbus_parent_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
-clk_mux_audio_err:
+clk_mux_audio_intbus_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
-clk_infra_sys_audio_err:
- clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
-clk_infra_audio_26m_err:
+clk_mux_audio_err:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
+clk_infra_audio_26m_err:
+ clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
+clk_infra_sys_audio_err:
return ret;
}
@@ -335,7 +353,9 @@ int mt8186_apll1_enable(struct mtk_base_afe *afe)
int ret;
/* setting for APLL */
- apll1_mux_setting(afe, true);
+ ret = apll1_mux_setting(afe, true);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
if (ret) {
@@ -360,9 +380,9 @@ int mt8186_apll1_enable(struct mtk_base_afe *afe)
return 0;
err_clk_apll1_tuner:
- clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
-err_clk_apll22m:
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
+err_clk_apll22m:
+ apll1_mux_setting(afe, false);
return ret;
}
@@ -388,7 +408,9 @@ int mt8186_apll2_enable(struct mtk_base_afe *afe)
int ret;
/* setting for APLL */
- apll2_mux_setting(afe, true);
+ ret = apll2_mux_setting(afe, true);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
if (ret) {
@@ -413,9 +435,9 @@ int mt8186_apll2_enable(struct mtk_base_afe *afe)
return 0;
err_clk_apll2_tuner:
- clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
-err_clk_apll24m:
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
+err_clk_apll24m:
+ apll2_mux_setting(afe, false);
return ret;
}
@@ -498,7 +520,7 @@ int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[m_sel_id], ret);
- return ret;
+ goto ERR_ENABLE_MCLK;
}
ret = clk_set_parent(afe_priv->clk[m_sel_id],
afe_priv->clk[apll_clk_id]);
@@ -506,7 +528,7 @@ int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[m_sel_id],
aud_clks[apll_clk_id], ret);
- return ret;
+ goto ERR_SELECT_MCLK;
}
}
@@ -515,16 +537,25 @@ int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[div_clk_id], ret);
- return ret;
+ goto ERR_ENABLE_MCLK_DIV;
}
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
__func__, aud_clks[div_clk_id], rate, ret);
- return ret;
+ goto ERR_SET_MCLK_RATE;
}
return 0;
+
+ERR_SET_MCLK_RATE:
+ clk_disable_unprepare(afe_priv->clk[div_clk_id]);
+ERR_ENABLE_MCLK_DIV:
+ERR_SELECT_MCLK:
+ if (m_sel_id >= 0)
+ clk_disable_unprepare(afe_priv->clk[m_sel_id]);
+ERR_ENABLE_MCLK:
+ return ret;
}
void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
index aced8e7e920c..1cff2a63ef37 100644
--- a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
@@ -143,6 +143,7 @@ static int mt8186_afe_gpio_adda_dl(struct device *dev, bool enable)
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_ON);
if (ret) {
dev_dbg(dev, "%s(), MOSI DAT ON select fail!\n", __func__);
+ mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_OFF);
return ret;
}
} else {
@@ -154,7 +155,8 @@ static int mt8186_afe_gpio_adda_dl(struct device *dev, bool enable)
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_OFF);
if (ret) {
- dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__);
+ dev_dbg(dev, "%s(), MOSI CLK OFF select fail!\n", __func__);
+ mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_ON);
return ret;
}
}
@@ -176,6 +178,7 @@ static int mt8186_afe_gpio_adda_ul(struct device *dev, bool enable)
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_ON);
if (ret) {
dev_dbg(dev, "%s(), MISO DAT ON select fail!\n", __func__);
+ mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_OFF);
return ret;
}
} else {
@@ -188,6 +191,7 @@ static int mt8186_afe_gpio_adda_ul(struct device *dev, bool enable)
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_OFF);
if (ret) {
dev_dbg(dev, "%s(), MISO CLK OFF select fail!\n", __func__);
+ mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_ON);
return ret;
}
}
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-pcm.c b/sound/soc/mediatek/mt8186/mt8186-afe-pcm.c
index 44a521c3a610..4bf098657fb4 100644
--- a/sound/soc/mediatek/mt8186/mt8186-afe-pcm.c
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-pcm.c
@@ -2743,7 +2743,11 @@ static int mt8186_afe_runtime_resume(struct device *dev)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
- regcache_sync(afe->regmap);
+ ret = regcache_sync(afe->regmap);
+ if (ret) {
+ regcache_cache_only(afe->regmap, true);
+ return ret;
+ }
/* enable audio sys DCM for power saving */
regmap_update_bits(afe_priv->infracfg, PERI_BUS_DCM_CTRL, BIT(29), BIT(29));
@@ -2848,10 +2852,8 @@ static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)
/* init audio related clock */
ret = mt8186_init_clock(afe);
- if (ret) {
- dev_err(dev, "init clock error, ret %d\n", ret);
+ if (ret)
return ret;
- }
/* init memif */
afe->memif_32bit_supported = 0;
@@ -2881,15 +2883,14 @@ static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)
/* request irq */
irq_id = platform_get_irq(pdev, 0);
- if (irq_id <= 0)
- return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO,
- "no irq found");
+ if (irq_id < 0)
+ return irq_id;
ret = devm_request_irq(dev, irq_id, mt8186_afe_irq_handler,
IRQF_TRIGGER_NONE,
"Afe_ISR_Handle", (void *)afe);
if (ret)
- return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
+ return ret;
ret = enable_irq_wake(irq_id);
if (ret < 0)
@@ -2953,10 +2954,8 @@ static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)
&mt8186_afe_component,
afe->dai_drivers,
afe->num_dai_drivers);
- if (ret) {
- dev_err(dev, "err_dai_component\n");
+ if (ret)
goto err_pm_disable;
- }
ret = pm_runtime_put_sync(dev);
if (ret) {
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-21 01:37:40 +0000