diff options
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a78000.dtsi | 59 |
1 files changed, 34 insertions, 25 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index fb71974ef390..1fe078c7822c 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include <dt-bindings/clock/renesas,r8a78000-cpg.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -668,23 +669,6 @@ }; }; - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <266660000>; - }; - extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -882,7 +866,9 @@ "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0700000 0 0x40>; interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -892,7 +878,9 @@ "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0704000 0 0x40>; interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -902,7 +890,9 @@ "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc0708000 0 0x40>; interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -912,7 +902,9 @@ "renesas,rcar-gen5-scif", "renesas,scif"; reg = <0 0xc070c000 0 0x40>; interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -922,7 +914,9 @@ "renesas,rcar-gen5-hscif", "renesas,hscif"; reg = <0 0xc0710000 0 0x60>; interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -932,7 +926,9 @@ "renesas,rcar-gen5-hscif", "renesas,hscif"; reg = <0 0xc0714000 0 0x60>; interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -942,7 +938,9 @@ "renesas,rcar-gen5-hscif", "renesas,hscif"; reg = <0 0xc0718000 0 0x60>; interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -952,7 +950,9 @@ "renesas,rcar-gen5-hscif", "renesas,hscif"; reg = <0 0xc071c000 0 0x60>; interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>, + <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; @@ -965,6 +965,15 @@ ranges = <0 0x0 0xc1060000 0x1c00>; /* actual transport nodes must be set per board file */ }; + + cpg: clock-controller@c1320000 { + compatible = "renesas,r8a78000-cpg"; + reg = <0 0xc1320000 0 0x10000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <1>; + bootph-all; + }; }; timer { |