summaryrefslogtreecommitdiff
path: root/arch/arm
AgeCommit message (Collapse)Author
28 hoursMerge branch 'headers' of git://git.infradead.org/users/willy/pagecache.gitMark Brown
# Conflicts: # net/ceph/osd_client.c
28 hoursMerge branch 'usb-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
29 hoursMerge branch 'master' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
29 hoursMerge branch 'master' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
29 hoursMerge branch 'for-next' of https://github.com/Xilinx/linux-xlnx.gitMark Brown
29 hoursMerge branch 'ti-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
29 hoursMerge branch 'sunxi/for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
29 hoursMerge branch 'stm32-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
29 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git
29 hoursMerge branch 'next' of https://github.com/Broadcom/stblinux.gitMark Brown
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
30 hoursMerge branch 'mm-nonmm-unstable' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
30 hoursMerge branch 'fixes' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git
30 hourssoc: document mergesArnd Bergmann
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
37 hoursinit, arch: make CONFIG_COMMAND_LINE_SIZE globally configurableWilson Felipe Pereira
Currently, s390 has the ability to configure the maximum kernel command line size via Kconfig (CONFIG_COMMAND_LINE_SIZE). Other architectures define a hardcoded COMMAND_LINE_SIZE macro in their setup.h headers. In some use cases, such as netboot kernels, rootfs configurations, or larger initramfs setups, a larger command line size is required. While for embedded workloads, it can be reduced to save memory. Move CONFIG_COMMAND_LINE_SIZE out of arch/s390/Kconfig and into init/Kconfig under General setup, and update every architecture's setup.h header to define COMMAND_LINE_SIZE as CONFIG_COMMAND_LINE_SIZE. For user-space API (uapi) headers, wrap the definition in an `#ifdef __KERNEL__` guard and retain the historical hardcoded default in the `#else` block. When user-space headers are installed via `make headers_install`, unifdef strips out the kernel section, ensuring the same value as before for user-space applications including `<asm/setup.h>`. For S390, the range is kept the same, but other architectures have varying constraints. S390 requires a minimum of 896 bytes to protect legacy bootloaders from overwriting the .text section. ARM, M68K, and NIOS2 allocate the command line directly on severely constrained decompressor stacks, so their ranges are strictly capped at 2048 bytes to prevent deterministic stack exhaustion and boot panics. PowerPC (PPC) boot wrappers silently truncate arguments past 2048 bytes, so it is also capped at 2048 to prevent silent parameter loss. The SuperH (SUPERH) boot parameter page allocates exactly PAGE_SIZE (typically 4096 bytes), and placing a 4096-byte command line starting at offset 256 would cause strscpy() to read out of bounds; it is capped at 3840 bytes. Alpha physically limits its boot parameter block to 256 bytes, so its limit is strictly locked to 256. All other architectures are capped at 4096 bytes to prevent unreasonable allocations. Link: https://lore.kernel.org/20260818231646.804507-2-wfelipe@google.com Signed-off-by: Maciej Żenczykowski <maze@google.com> Signed-off-by: Wilson Felipe Pereira <wfelipe@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com>
3 daysMerge branches 'imx/drivers', 'imx/dt' and 'imx/dt64' into for-nextFrank Li
3 daysARM: dts: imx53: drop fallback compatible "dlg,da9052"Frank Li
The "dlg,da9053-aa" compatible string is not compatible with "dlg,da9052". DA9052 vs DA9053-AA Differences (from da9052-regulator.c) 1. BUCK4 Voltage Range (only regulator table difference) DA9052 BUCK4 DA9053-AA BUCK4 Min voltage 1800 mV 950 mV Max voltage 3600 mV 2525 mV Step size 50 mV 25 mV DA9052 BUCK4 also has a non-linear voltage mapping above 3V (step increases to 100 mV for selector >= 24). DA9053-AA BUCK4 has no such special mapping. 2. BUCK Current Limits Level DA9052 (all BUCKs) DA9053-AA BUCK1 DA9053-AA BUCK2/3/4 0 700 mA 1600 mA 800 mA 1 800 mA 2000 mA 1000 mA 2 1000 mA 2400 mA 1200 mA 3 1200 mA 3000 mA 1500 mA DA9053-AA BUCK1 supports up to 3A (vs 1.2A on DA9052). Drop the fallback compatible to fix the following CHECK_DTBS warning: dialog@48 (dlg,da9053-aa): compatible: ['dlg,da9053-aa', 'dlg,da9052'] is too long Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx6ul-14x14-evk: remove reduntant bus-type under csi nodeFrank Li
Remove reduntant undocument bus-type under csi node to fix below check_dtbs warnings: arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtb: csi@21c4000 (fsl,imx6ul-csi): port:endpoint: Unevaluated properties are not allowed ('bus-type' was unexpected) from schema $id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml buy-type already set at remote endpoint ov5640_to_parallel. Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx6sll: remove unused node csi@20e8000Frank Li
csi@20e8000 is never used with compatible string 'fsl,imx6s-csi'. Remove it to fix the below check_dtb warnings: arch/arm/boot/dts/nxp/imx/imx6sll-evk.dtb: /soc/bus@2000000/csi@20e8000: failed to match any schema with compatible: ['fsl,imx6sll-csi', 'fsl,imx6s-csi'] Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx6dl-b125v2: add touchscreen-size-x/y to exc80h60 nodeFrank Li
The eeti,exc3000 binding requires touchscreen-size-x and touchscreen-size-y properties. Add them for both the B125v2 and B125Pv2 boards, which use the AUO G121EAN01 panel at 1280x800 resolution. Fix below check_dtbs warnings: arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dtb: touchscreen@2a (eeti,exc80h60): 'touchscreen-size-x' is a required property Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx50-kobo-aura: convert sd2_vmmc to regulator-fixedFrank Li
The sd2_vmmc regulator was using compatible = "regulator-gpio" with only a single state entry (states = <3300000 0>), which violates the gpio-regulator DT schema that requires at least two state pairs. Since the regulator operates at a fixed 3.3 V (regulator-min-microvolt equals regulator-max-microvolt), convert the node to regulator-fixed. Fix below check_dtbs warnings: arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dtb: gpio-regulator (regulator-gpio): states: [[3300000, 0]] is too short Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx7d-meerkat96: disable lcdif nodeFrank Li
The LCDIF node is enabled, but no display panel is connected through the required graph bindings. As a result, the LCDIF DT description is incomplete and triggers DT schema validation warnings. arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dtb: lcdif@30730000 (fsl,imx7d-lcdif): 'port' is a required propert Disable the LCDIF node until a proper panel node and display pipeline are added to fix above warnings. Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx7d-nitrogen7: drop unsupported wakeup-gpios from tsc2004Frank Li
Remove undocumented and used property wakeup-gpios, which is the same as interrupts-extended. Fix below check_dtbs warning: arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dtb: touchscreen@48 (ti,tsc2004): 'wakeup-gpios' does not match any of the regexes: '^pinctrl-[0-9]+$' No known other user use wakeup-gpios. Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx6qdl-emcon: Remove unrecognized disable-gpio PCIe propertyFrank Li
The 'disable-gpio' property is not defined in the fsl,imx6q-pcie binding schema and driver code, which causes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dtb: pcie@1ffc000 (fsl,imx6q-pcie): Unevaluated properties are not allowed ('disable-gpio' was unexpected) from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysARM: dts: imx51-zii-rdu1: rename node name i2c-gpio to i2c-0Frank Li
The binding expects the node name to match the pattern '^i2c(@.+|-[a-z0-9]+)?$', but the node was named 'i2c-gpio' which conflicts with schema validation and produces: arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dtb: / (zii,imx51-rdu1): i2c-gpio: {'compatible': ['i2c-gpio'], 'pinctrl-names': ['default'], 'pinctrl-0': [[47]], 'sda-gpios': [[17, 2, 0]], 'scl-gpios': [[31, 4, 0]], 'i2c-gpio,delay-us': [50], 'status': ['okay'], '#address-cells': 1, '#size-cells': 0, 'codec@a': {'compatible': ['fsl,sgtl5000'], 'reg': [[10]], 'clocks': [[48]], 'VDDA-supply': [[49]], 'VDDIO-supply': [[50]], '#sound-dai-cells': 0, 'phandle': 57}} is not of type 'array' Rename the node to 'i2c-0' to fix above dtbs_check warning. Assisted-by: Claude:claude-sonnet-4.6 Signed-off-by: Frank Li <Frank.Li@nxp.com>
3 daysMerge branches 'renesas-arm-defconfig-for-v7.4', 'renesas-drivers-for-v7.4' ↵Geert Uytterhoeven
and 'renesas-dts-for-v7.4' into renesas-next
3 daysARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable GPIOs on CN12Wolfram Sang
CN12 offers some GPIOs independently of switch settings. Add the nodes. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260817103255.49565-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: Correct white-space styleKrzysztof Kozlowski
Correct a few white-space issues, like using tab after ':' character or spurious space before '{', which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260801210321.383773-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: r9a06g032: Don't set status to the default valueWolfram Sang
"okay" is the default for 'status', so don't encode it explicitly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260716101030.15252-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: r9a06g032-rzn1d400: Don't enable gpiochips which are ↵Wolfram Sang
always on gpiochips are always enabled, no need to enable them explicitly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260716095935.13329-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: lager: Use inclusive wordingWolfram Sang
The feature is now officially called "target" in I2C documentation. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260715105306.25147-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: lager: Specify correct connector for i2cexio0 busWolfram Sang
It is located on EXIO connector C, not A. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260715105306.25147-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: sk-rzg1e: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-9-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: sk-rzg1m: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-8-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: silk: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-7-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: alt: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-6-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: gose: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: porter: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: koelsch: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: stout: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: lager: Specify ethernet PHY reset timingsMarek Vasut
The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for the same value as used for KSZ9031RNX, which is 300 us. The KSZ8041RNL reference manual [1] DS00002245C page 47 TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS row tSR Stable supply voltages to reset high is at minimum 10 ms. Set the DT property reset-assert-us to 10ms because the KSZ8041RNL RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8041NL-RNL-Data-Sheet-DS00002245.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130429.11214-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: armadillo800eva: Specify ethernet PHY reset timingsMarek Vasut
The LAN8710Ai reference manual [1] DS00002164C page 61 FIGURE 5-3: POWER-ON NRST & CONFIGURATION STRAP TIMING does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for 300 us which should cover every timing option, including the 16 us delay required for MDIO to switch to 25 MHz listed in Note: in Chapter 3.8.5 RESETS. The LAN8710Ai reference manual [1] DS00002164C page 61 TABLE 5-8: POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES row tSR Stable supply voltages to reset high is at minimum 10 ms. Set DT property reset-assert-us to 25ms because the LAN8710Ai RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN8710A-LAN8710Ai-Data-Sheet-DS00002164.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130325.11080-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 daysARM: dts: renesas: gr-peach: Specify ethernet PHY reset timingsMarek Vasut
The LAN8710Ai reference manual [1] DS00002164C page 61 FIGURE 5-3: POWER-ON NRST & CONFIGURATION STRAP TIMING does not indicate how long should the system wait after deassertion of the PHY reset and before start of communication with the PHY via MDIO. Opt for 300 us which should cover every timing option, including the 16 us delay required for MDIO to switch to 25 MHz listed in Note: in Chapter 3.8.5 RESETS. The LAN8710Ai reference manual [1] DS00002164C page 61 TABLE 5-8: POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES row tSR Stable supply voltages to reset high is at minimum 10 ms. Set DT property reset-assert-us to 25ms because the LAN8710Ai RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/LAN8710A-LAN8710Ai-Data-Sheet-DS00002164.pdf Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260714130325.11080-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-17 17:32:18 +0000