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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
13 hoursclk: renesas: Make sure clk_init_data is fully initializedGeert Uytterhoeven
34 hoursclk: renesas: r9a08g046: Add clock and reset entries for LVDSBiju Das
34 hoursclk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entriesBiju Das
34 hoursclk: renesas: r9a08g046: Sort macro definitions alphabeticallyBiju Das
34 hoursclk: renesas: rzg2l: Add support for RZ/G3L DSI muxBiju Das
34 hoursclk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty ...Biju Das
34 hoursclk: renesas: rzg2l: Add support for divider flagsBiju Das
34 hoursclk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flagsBiju Das
34 hoursclk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3LBiju Das
34 hoursclk: renesas: rzg2l: Add DSI divider clock support for RZ/G3LBiju Das
34 hoursclk: renesas: Clean-up simple provider misuse of the consumer APIJerome Brunet
12 daysMerge branches 'clk-pile' and 'clk-microchip' into clk-nextStephen Boyd
2026-08-17Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pileStephen Boyd
2026-08-06clk: renesas: Add R-Car X5H CPG driverGeert Uytterhoeven
2026-08-05Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3Geert Uytterhoeven
2026-07-13clk: r9a08g045: Add clocks and resets for CAN-FDClaudiu Beznea
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c f...Uwe Kleine-König (The Capable Hub)
2026-06-30clk: renesas: r9a09g047: Add LVDS clocks and resetsTommaso Merciai
2026-06-30clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display p...Lad Prabhakar
2026-06-30clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared libraryLad Prabhakar
2026-06-30clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculationsLad Prabhakar
2026-06-30clk: renesas: r9a08g046: Add USB2.0 clock and reset entriesBiju Das
2026-06-30clk: renesas: r9a09g077: Add RTC clocksLad Prabhakar
2026-06-30clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC ...Lad Prabhakar
2026-06-30clk: renesas: r9a08g046: Add clock and reset entries for GE3DBiju Das
2026-06-30clk: renesas: r9a08g046: Add clock and reset entries for SDHIBiju Das
2026-06-30clk: renesas: r9a09g047: Add audio clock and reset supportJohn Madieu
2026-06-29clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()Brian Masney
2026-05-28clk: renesas: r9a08g045: Drop unused pm_domain header fileBiju Das
2026-05-28clk: renesas: r8a779g0: Add DSC clockMarek Vasut
2026-05-25clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowingLad Prabhakar
2026-05-25clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macroLad Prabhakar
2026-05-22clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed onesBiju Das
2026-05-22clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macroBiju Das
2026-05-22clk: renesas: rzg2l: Simplify SAM PLL configuration macroBiju Das
2026-05-15clk: renesas: r8a73a4: Add ZT/ZTR trace clocksMarek Vasut
2026-05-11clk: renesas: r9a08g046: Add RSPI clocks and resetsBiju Das
2026-05-11clk: renesas: r9a08g046: Add SSIF-2 clocks and resetsBiju Das
2026-05-11clk: renesas: r9a08g046: Add RSCI clocks and resetsBiju Das
2026-05-07clk: renesas: cpg-mssr: Add number of clock cells checkGeert Uytterhoeven
2026-05-07clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()Geert Uytterhoeven
2026-05-07clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()Geert Uytterhoeven
2026-05-07clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocksBiju Das
2026-05-04Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2Geert Uytterhoeven
2026-05-04clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resetsTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add support for DSI clocks and resetsTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLKTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocksTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocksTommaso Merciai
2026-05-04clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocksTommaso Merciai