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path: root/drivers/gpu
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2026-08-25drm/amd/display: Refactor HUBP_WAIT_FOR_DCC_META_PROP to drop pipe_ctxTomasz Siemek
[why] Pipe_ctx shouldn't be passed as block sequence block parameter. [how] Precalculate delay during building stage instead during execution. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Send DPM0 clock values to DMUOvidiu Bunea
[why & how] Z8 Retention requires clocks to be put into bypass for the PLL to be powered down. Notify DMU of the DPM0 clock values, which is likely always going to be running of a bypass clock. Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Notify DMU to allow DCHVM<->rIOMMU SDP port disconnection ↵Ovidiu Bunea
for DCN42 [why & how] Allowing the DCHVM<->rIOMMU SDP port to disconnect during IPS1 cycling can cause extra credits to be released to rIOMMU. In turn, this will let the rIOMMU issue more outstanding table walk requests at once, overflowing the downstream request FIFO. This results in dropped/orphaned requests with no method of recovery. This typically manifests as an invalidation hang error in the main IOMMU. As a workaround, dis-allow the SDP port from disconnecting from IPS1 exit up until after powerstatus=1. This ensures that rIOMMU does not have the chance to request credits multiple times during the powerstatus 0->1 transition. Since x86 driver cannot access rIOMMU register space, send a command to DMU to do it. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add utm_support capability flagWenjing Liu
[Why] Expose whether the ASIC supports Universal Traffic Management so upper layers can query the capability instead of assuming support. [How] Add a new bool capability field to dc_caps, defaulting to false, and set it to true during DCN6 resource construction. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Rename carried dce clock manager functions for dcn10Dillon Varone
[WHY&HOW] Some legacy DCE functions were carried over to DCN10 and later. These functions are now renamed to remove the DCE prefix and be more generic. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Guard against empty DCN6 UTM QoS tableWenjing Liu
[Why] The UTM QoS model population indexed into a firmware-provided table without checking whether it reported any load levels or SOPs, leaving a malformed table treated as valid instead of absent. [How] Bail out early and clear the output model pointer when the load level count or SOP count is zero. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add DC_BLS commandOvidiu Bunea
[why & how] In the future, DC will off-load block-level initialization to DMUB. In preparation, update dmub_cmd.h with the command for better tracking. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: set base.enable in cursor mode testsTom Chung
[why] The CRTC state in the amdgpu_dm_crtc_get_cursor_mode() tests is zero-initialised, so base.enable is false in all of them. Nothing in the function reads it today, so they pass, but they are not describing the case they mean to describe: each one is meant to exercise an enabled CRTC driving real planes. [how] Set base.enable in the shared fixture, and in the no_change test which builds its own CRTC state instead of using the fixture. No functional change, since the function does not look at base.enable yet. Reviewed-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test native cursor mode on a disabled CRTCTom Chung
[why] Upstream has no KUnit coverage for amdgpu_dm_crtc_get_cursor_mode(), which is why the fix in the previous commit came with no test. The disabled-CRTC path is easy to regress again: it has already been lost once to a refactor. [how] Add a test whose plane setup would otherwise select overlay mode, and check that a disabled CRTC still reports native mode. Reverting the previous commit makes only this test fail. Reviewed-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Move periodic interrupt calculations to HWSSTomasz Siemek
[why] Periodic interrupt line calculations depends on stream and pipe state, not ASIC-specific register programming. Keeping it in the DCN10 implementation also prevents block-sequence callers from carrying fully resolved parameters. We want HWSS block parameters to not include complex structures like pipe_ctx. [how] - Move the vertical interrupt line calculation into common HWSS code. - Update the periodic interrupt callback. - Calculate the values before direct or block-sequence execution. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add CACP ACE curve area debugfs for IGT validationChenyu Chen
[Why] IGT test cases for CACP need a way to validate that the ACE (Adaptive Contrast Enhancement) curve responds to the CACP aggression level. No interface exists to read the resulting curve back from firmware for automated validation. [How] Add a read-only "cacp_ace_curve_area" debugfs node on eDP connectors that support CACP. It issues a DMUB_CMD__CACP_GET_ACE_CURVE_AREA command and reports the area under the ACE PWL curve returned by firmware, which is directly comparable across CACP levels, so IGT tests can query it per panel. Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: JPEG 5_0_2 enable multi-instanceSonny Jiang
Enable JPEG 5_0_2 multi-instance. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Jpeg uses shard VM invalidation engineSonny Jiang
JPEG 5_0_2 has 2 instances per die. Each instance has 10 rings. Each ring consuming a unique VM invalidation engine exhausts the available engines per MMHUB. All rings within a JPEG instance can safely share one engine since MMHUB serializes concurrent invalidation requests via hardware semaphore (see "drm/amdgpu: add invalidate semaphore support for gmc v12.1"). Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Jpeg 5_0_2 enable doorbellSonny Jiang
Enable JPEG 5_0_2 doorbell Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: JPEG 5_0_2 set inst_per_aid to 2Sonny Jiang
JPEG 5.0.2 has 2 JPEG instances per MID. Report 2 JPEG instances per AID Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: VCN 5_0_2 correct process interrupt warn messageSonny Jiang
Fix the incorrect interrupt process warning message. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: JPEG 5_0_2 Add multi-instance interrupt supportSonny Jiang
JPEG 5.0.2 has two JPEG instances per MID. Register JPEG interrupt sources for both VCN IH clients and add a JPEG 5.0.2-specific interrupt handler. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: VCN 5_0_2 enable multi-instanceSonny Jiang
Remove forcing the VCN instance mask to a single instance during soc_v1_0 SOC setup. Use the configured instance mask so multi-instance VCN 5.0.2 topologies can be enabled. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: VCN 5_0_2 disable VCN_RRMTSonny Jiang
When RRMT is enabled, VCN firmware's register access is remapped so that VCN instances on different dies (VCN0/1 on MID0, VCN2/3 on MID1) require different target addresses for the same logical register. Remove the RRMT capability detection so the driver always assumes RRMT is disabled, using local-die SMN addresses for all instances. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: VCN 5_0_2 add support for multi-instanceSonny Jiang
VCN 5.0.2 has two VCN instances per MID. Update the SOC configuration and VCN 5.0.2 initialization to handle multiple instances Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Correct VCN V5_0_2 doorbell index settingSonny Jiang
Each VCN 5.0.2 instance has 11 doorbells. Use an 11-doorbell when calculating the per-instance VCN ring doorbell index. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: correct VCN V5_0_2 doorbell range_sizeSonny Jiang
Each VCN 5.0.2 instance has 1 VCN ring and 10 JPEG rings, requiring 11 consecutive doorbells. Increase the NBIO doorbell range size from 8 to 11 to cover the full ring set. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Config JPEG instance for soc_v1_0Sonny Jiang
Set up the default JPEG instance mask and related instance counts during soc_v1_0 SOC configuration, before IP discovery is enabled. Signed-off-by: Sonny Jiang <sonjiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: do not fail hw_init on ras eeprom errorsTao Zhou
Even if eeprom is not functional, other RAS functions can still work, no need to block the whole driver initialization. Previously-retired bad pages are no longer loaded when ras_core_eeprom_recovery() fails, so the GPU keeps using known-bad memory; New bad pages cannot be persisted as well. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Config VCN instance for soc_v1_0"Sonny Jiang
Set up the default VCN instance mask and related instance counts during soc_v1_0 SOC configuration, before IP discovery is enabled. Signed-off-by: Sonny Jiang <sonjiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Bump version for userq timeline syncobj fixesDavid Rosca
Contains fix for userq waiting on timeline syncobjs and adds userq support for signaling timeline syncobjs. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David Rosca <david.rosca@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu/userq: Add syncobj_points to signal ioctlDavid Rosca
Userspace patches: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 Signed-off-by: David Rosca <david.rosca@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: set pa base and lfb size for unirasTao Zhou
Avoid hardcode, get the parameters from amdgpu(retire SOCKET_LFB_SIZE macro). For the algorithms of ras address conversion and get_die_id, not only pa, (pa + pa_base) is also needed. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu/ttm: Make buffer copy source readonlyTimur Kristóf
When amdgpu is moving a BO from a location in VRAM to another location in VRAM, we map both BOs in the GART and perform the copy operation using the GART addresses. We are not writing into the first GART window, so let's set the PTE flags to make it readonly. This doesn't fix any known issues but let's do it just to be safe. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: Remove unused functions in smu_v15_0Srinivasan Shanmugam
smu_v15_0_load_microcode() and smu_v15_0_set_single_dpm_table() are not called anywhere; the latter is a carry-over from a previous version. The static helpers smu_v15_0_get_dpm_freq_by_index(), smu_v15_0_get_dpm_level_count() and smu_v15_0_get_fine_grained_status() were only called from smu_v15_0_set_single_dpm_table(), so remove those as well. Remove all functions along with their declarations from the header. Fixes: c7fc0f372374 ("drm/amd: Enable SMU 15_0_0 support") Fixes: f7bee962d92a ("drm/amd/pm: Update dpm table structs for smu_v15_0") Reported-by: Dan Carpenter <error27@gmail.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: compute SMU v15.0.0 gpu_metrics from accumulator tableShubhankar Milind Sardeshpande
Rework smu_v15_0_0_get_gpu_metrics() to derive values from the raw accumulator double-buffer instead of the firmware-computed SmuMetrics_t snapshot: - Add SMU_V15_IOD_AVG()/SMU_V15_CORE_AVG() helpers: wrapping_sub() delta over the sampling window, scaled by the caller's unit factor, then descaled from Q10 fixed-point with >>10 (scale before shift to keep sub-unit precision); typeof() preserves each field's width. - Reuse the same macro in smu_v15_0_0_compute_all_metrics(), dropping the open-coded div_u64(..., 1024) boilerplate. - Drop the unused smu_v15_0_0_get_gpu_metrics_table() helper and the SMU_TABLE_SMU_METRICS allocation. Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Assisted-by: Claude:claude-opus-4.8 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Promote DC to 3.2.393Taimur Hassan
This DC patchset brings improvements in multiple areas. In summary, we have: * DCN6 fixes on GPUVM calculations, HostVM and SOCBB VM config, clkmgr interfaces, and peak bandwidth measurement * HDMI FRL fixes on LT timeout behaviour and cap restore during non-destructive link verify * Greatly enhanced KUnit coverage across CRTC, VRR, and cursor paths * eDP panel polarity control, FreeSync range quirk, and Z8-based zstate support * DCE ASIC code gated behind CONFIG_DRM_AMD_DC_DCE for DCN-only builds * Fixes on HPD filter programming, DMUB DIG PHY wait, dcn42b force_min_dcfclk clamp, audio tests, and UTM client QC profile override Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: restore FRL cap on non-destructive HDMI link verifyFangzhi Zuo
[Why&How] Restore the FRL verified cap from the reported cap so a link whose FRL pre-training was skipped (e.g. skip_frl_pre_training) stays on FRL across a hotplug instead of falling back to TMDS. On hotplug the HDMI sink is recreated as SIGNAL_TYPE_HDMI_TYPE_A and only the destructive verify path promotes it to FRL via hdmi_frl_verify_link_cap(). When the non-destructive path runs - which is what the skip_frl_pre_training quirk forces on an already-active link - the HDMI branch mistakenly assigned the DP verified_link_cap from reported_link_cap and left frl_verified_link_cap stale. With frl_link_rate reading back as HDMI_FRL_LINK_RATE_DISABLE, the stream collapsed to TMDS. Assign frl_verified_link_cap from frl_reported_link_cap (populated during detection by hdmi_frl_retrieve_link_cap()) to match the reference DM behavior and keep the link on FRL. Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Fix DCN6 peak bandwidth measurement overshootWenjing Liu
[Why] The out-of-order (peak prefetch) bandwidth probe could report bandwidth far above the physical clock ceiling. The data and duration counters could latch on different edges of the shared stop event, and very short measurement windows amplified refclk tick quantization into large relative errors. [How] Add a dedicated counter (2) that generates the single stop event both the data counter (1) and duration counter (4) key off of, so they always latch on the same edge. Reject samples where the data counter overshoots the generator's target, or where the duration is too short to trust. Also drop the single-timing-group restriction on the peak-BW probe. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Apply workaround to limit SopCount for nowAlvin Lee
[Description] - PMFW does not populate the SopCount correctly today. For now limit to 5 since that's the default number of populated array entries for the Sop array in PMFW. - Also remove some commented out code Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Align KUnit tests Makefile license headerRay Wu
[Why & How] Use GPL-2.0 OR MIT and Copyright 2026 to match other KUnit test files. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Update dcn60 clkmgr interfacesAlvin Lee
[Description] Update clk_mgr interfaces to match with the DAL<->PMFW message interfaces for DCN6. - dalsmc.h MAX_PPCLK_COUNT must match PPCLK count in driver_if header - include driver_if header as a local copy for now since PMFW carried one will not build - clk table returned by PMFW is in Khz, must convert to Mhz accordingly - boot snapshot for dispclk is in Khz - Get*Clk interfaces should return frequency in Khz, ensure that DAL interfaces are implemented to handle this - Move structure definitions into dcn60_clk_mgr_smu_msg.h header since the official dalsmc.h header does not carry all these definitions yet Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Force FreeSync range minimum on quirky panelsFangzhi Zuo
[why] Some panels advertise a FreeSync range minimum that does not operate reliably at the low end: - X34GS (EDID panel id ACR 0x08AF) reports a minimum that can flicker or drop out when the refresh rate approaches the reported minimum. - 34w-30 (EDID panel id LEN 0x66F1) reports a 48 Hz minimum over DisplayPort, but the panel fails to light up at that minimum, resulting in a black screen. Forcing the minimum to 60 Hz avoids the black screen and lets the display light up normally. [how] - Add a force_freesync_min_hz field to struct dc_panel_patch. - Add apply_edid_quirks() cases keyed on the affected panel ids that set force_freesync_min_hz (55 Hz for the X34GS, 60 Hz for the G34w-30). - In amdgpu_dm_update_freesync_caps(), when the quirk is set and the sink is otherwise FreeSync capable, clamp the reported VRR range minimum (min_vfreq and monitor_range.min_vfreq) to the quirked value. - Add a KUnit test covering the new quirk. Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test amdgpu_dm_crtc_get_cursor_modeAlex Hung
[WHAT] Add KUnit tests for amdgpu_dm_crtc_get_cursor_mode() with a synthetic two-plane atomic-state fixture, an invocation helper, and a colorop helper, covering: - new hardware defaulting to overlay mode, - an unchanged state keeping native mode, - a disabled cursor keeping native mode, - a YUV underlying plane forcing overlay, - a plane scale mismatch forcing overlay, - full cursor coverage allowing native mode, - a coverage hole forcing overlay, - an unrelated update leaving the cursor untouched, - a cursor scale change forcing recomputation, - a cursor position change forcing recomputation, - a color pipeline activation forcing recomputation. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test dm_plane_color_pipeline_activeAlex Hung
[WHAT] Add two KUnit tests for dm_plane_color_pipeline_active(): one confirming an active pipeline is detected, and one confirming colorops on an unrelated plane are ignored. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test native cursor state checkAlex Hung
[WHAT] Add three KUnit tests for amdgpu_dm_check_native_cursor_state(), reusing the cursor framebuffer fixture, covering the disabled-cursor path, rejection of a non-zero source offset, and delegation to the framebuffer check. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test dm_check_cursor_fbAlex Hung
[WHAT] Add nine KUnit tests for dm_check_cursor_fb() with a cursor framebuffer fixture, covering the supported linear case, size, cropping and pitch rejections, tiling handling across ASIC generations, and modifier-based tiling skips. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Extend DMUB wait for DIG PHY programming commandsWayne Lin
[Why] DIG transmitter ENABLE and voltage/pre-emphasis VBIOS commands can take longer than the default inbox timeout after amdgpu reload, while DMCUB runs extended DPPHY polling before advancing INBOX1 RPTR. [How] Extend the waiting time to 500ms Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Update and revert FRL LT Timeout behaviourRelja Vojvodic
[Why & How] - Revert logic to fallback to polling if LT no timeout is set - Update LT timeout to 300ms for appropriate link rates Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test VRR transitionsAlex Hung
[WHAT] Add tests for amdgpu_dm_handle_vrr_transition() covering steady inactive state and an inactive-to-active-to-inactive vblank reference round trip. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test VRR IRQ parametersAlex Hung
[WHAT] Add tests for amdgpu_dm_update_stream_irq_parameters() covering stream and timing guards, unsupported configuration, and variable, inactive, and fixed VRR states. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: test stream VRR updatesAlex Hung
[WHAT] Add tests for amdgpu_dm_update_freesync_state_on_stream() covering stream and timing guards, packet updates, pre-AI adjustment, and PCON AMD VSDB packet selection. Assisted-by: Copilot:GPT-5.6-Sol Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Decide zstate_support based off Z8 global supportOvidiu Bunea
[why & how] DC incorrectly reports ZStates NOT supported for eDP panels without support for PSR or Replay. This is because the zstate_support flag is populated with supported_in_blank, which is not the correct interpretation. Z8 can be entered for a plane when its Z8 stutter enter plus exit time is covered either during vblank (reserved vblank time is greater than SREnterPlusExitZ8Time) or during vactive (active clock change latency hiding minus the Z8StutterEnterPlusExitWatermark is positive). Compute this per plane in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(), and report Z8 as supported only when every non-phantom plane satisfies at least one of these two cases. Populate z8_stutter.global_support in mode programming and use it to populate zstate_support. Assisted-by: Claude:claude-Opus-4.8 Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: gate DCE ASIC code behind CONFIG_DRM_AMD_DC_DCEGaghik Khachatrian
[Why&How] Refactor to make DCE support optional. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: eDP panel polarity control and test supportHarry VanZyllDeJong
eDP panels can require explicit polarity control during power transitions to ensure correct signal behavior. Without this, panels that depend on polarity state may behave incorrectly when combined with refresh rate drop logic, since the two features previously had no coordination point. To address this, a set/reset/query API is introduced and integrated into the resource layer so polarity is managed as a first-class concern within the existing power optimization flow. RamlessPowerOptimization is updated to coordinate polarity state alongside refresh rate drop decisions, preventing the two paths from conflicting during transitions. Reviewed-by: Sreeja Golui <sreeja.golui@amd.com> Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-09-20 22:43:34 +0000